diff options
| author | Atish Patra <atishp@rivosinc.com> | 2022-04-26 09:29:22 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-04-28 09:15:21 +0300 |
| commit | d62f6da062ad0fcc3bdc042a3f3b200d91d18afd (patch) | |
| tree | c26f03e59440fd15c0b6639633645dcd45114b76 /include/sbi/riscv_encoding.h | |
| parent | 4035ae94be802a68f8e8408a84b77f531d59416b (diff) | |
| download | opensbi-d62f6da062ad0fcc3bdc042a3f3b200d91d18afd.tar.xz | |
lib: sbi: Implement Sstc extension
Recently, Sstc extension was ratified. It defines stimecmp which allows
the supervisor mode to directly update the timecmp value without the
need of the SBI call. The hardware also can inject the S-mode timer
interrupt direclty to the supervisor without going through the M-mode.
To maintain backward compatibility with the older software, SBI call
now uses stimecmp directly if the hardware supports.
Implement the Sstc extension.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include/sbi/riscv_encoding.h')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index a9772a6..7cfbace 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -324,6 +324,10 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 +/* Sstc extension */ +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + /* Supervisor Protection and Translation */ #define CSR_SATP 0x180 |