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| author | Anup Patel <anup.patel@wdc.com> | 2020-08-18 10:58:08 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-09-01 07:58:28 +0300 |
| commit | 74d1db706293f42f5a4e87c907978339b2d0993d (patch) | |
| tree | 304eca12e33cb98ed1759eca70b41a0c2a8518f3 /include/sbi/sbi_hart.h | |
| parent | 7b0b289887380d2e71210f12b5ce0f3afc011b35 (diff) | |
| download | opensbi-74d1db706293f42f5a4e87c907978339b2d0993d.tar.xz | |
lib: sbi: Improve PMP CSR detection and progamming
As-per latest RISC-V privilege spec up to 64 PMP entries are supported.
Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR
fields are WARL and may be hardwired to zero.
This patch improves PMP CSR detection and progamming considering
above facts.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include/sbi/sbi_hart.h')
0 files changed, 0 insertions, 0 deletions