diff options
| author | Atish Patra <atish.patra@wdc.com> | 2020-05-10 02:47:30 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-05-10 07:44:54 +0300 |
| commit | ec0d2a7d7d8b78193375651627aa6f65b9219afe (patch) | |
| tree | 4a694ae1b74eb02f5bfb3aa4f2cd35ea93e63f9b /include/sbi/sbi_hart.h | |
| parent | 49380244202460aa2fd322dc9a3bdd79b388bf9d (diff) | |
| download | opensbi-ec0d2a7d7d8b78193375651627aa6f65b9219afe.tar.xz | |
lib: timer: Provide a hart based timer feature
As per the RISC-V specification, time value can be obtained from a time
CSR implemented in hardware or a MMIO based IP block. Qemu virt machine
already supports timer csr while CLINT provides the timer for other
platforms.
Implement a hart specific timer feature that can be detected at runtime.
As CSR based timer implementation are faster than MMIO address based, it
is always preferred over MMIO based one.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'include/sbi/sbi_hart.h')
| -rw-r--r-- | include/sbi/sbi_hart.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index f7870d9..beb61b6 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -20,6 +20,8 @@ enum sbi_hart_features { SBI_HART_HAS_SCOUNTEREN = (1 << 1), /** Hart has M-mode counter enable */ SBI_HART_HAS_MCOUNTEREN = (1 << 2), + /** HART has timer csr implementation in hardware */ + SBI_HART_HAS_TIME = (1 << 3), }; struct sbi_scratch; |