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| author | Anup Patel <anup.patel@wdc.com> | 2019-12-12 04:52:03 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-12-16 12:18:19 +0300 |
| commit | 4370f18f3467fee4a80fd463f1c0247d02f912d6 (patch) | |
| tree | 0f166f806818afe8d60db7fe1711693447f78dc1 /include/sbi/sbi_trap.h | |
| parent | 6590a7dab9d7182b659a13338043889350d9c6bb (diff) | |
| download | opensbi-4370f18f3467fee4a80fd463f1c0247d02f912d6.tar.xz | |
include: Extend struct sbi_trap_info for mtval2 and mtinst
We have two new trap CSRs namely mtval2 and mtinst when
RISC-V hypervisor extension is available hence we extend
struct sbi_trap_info accordingly.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/sbi/sbi_trap.h')
| -rw-r--r-- | include/sbi/sbi_trap.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/sbi/sbi_trap.h b/include/sbi/sbi_trap.h index 4baa3a5..9a35a6e 100644 --- a/include/sbi/sbi_trap.h +++ b/include/sbi/sbi_trap.h @@ -178,6 +178,10 @@ struct sbi_trap_info { unsigned long cause; /** tval Trap value */ unsigned long tval; + /** tval2 Trap value 2 */ + unsigned long tval2; + /** tinst Trap instruction */ + unsigned long tinst; }; struct sbi_scratch; |