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| author | Atish Patra <atish.patra@wdc.com> | 2019-02-13 05:32:06 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-02-14 07:01:18 +0300 |
| commit | 70a474d2c24dc3e0c8841e6ef5cc96797deadbf5 (patch) | |
| tree | 0c1456134e4815aadea0f523d7fb570454e23d0d /include/sbi/sbi_unpriv.h | |
| parent | 4cb4d46875dd0f0dd01d3ff1fee4f0d6cefb857a (diff) | |
| download | opensbi-70a474d2c24dc3e0c8841e6ef5cc96797deadbf5.tar.xz | |
lib: Use CSR_<FOO> instead of <foo> for csr_*()
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include/sbi/sbi_unpriv.h')
| -rw-r--r-- | include/sbi/sbi_unpriv.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/sbi/sbi_unpriv.h b/include/sbi/sbi_unpriv.h index 11ece0d..930babd 100644 --- a/include/sbi/sbi_unpriv.h +++ b/include/sbi/sbi_unpriv.h @@ -20,9 +20,9 @@ static inline type load_##type(const type *addr, ulong mepc) \ register ulong __mepc asm ("a2") = mepc; \ register ulong __mstatus asm ("a3"); \ type val; \ - asm ("csrrs %0, mstatus, %3\n" \ + asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ #insn " %1, %2\n" \ - "csrw mstatus, %0" \ + "csrw "STR(CSR_MSTATUS)", %0" \ : "+&r" (__mstatus), "=&r" (val) \ : "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc)); \ return val; \ @@ -33,9 +33,9 @@ static inline void store_##type(type *addr, type val, ulong mepc) \ { \ register ulong __mepc asm ("a2") = mepc; \ register ulong __mstatus asm ("a3"); \ - asm volatile ("csrrs %0, mstatus, %3\n" \ + asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ #insn " %1, %2\n" \ - "csrw mstatus, %0" \ + "csrw "STR(CSR_MSTATUS)", %0" \ : "+&r" (__mstatus) \ : "r" (val), "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc)); \ } @@ -76,18 +76,18 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus) register ulong __mstatus asm ("a3"); ulong val; #ifndef __riscv_compressed - asm ("csrrs %[mstatus], mstatus, %[mprv]\n" + asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n" #if __riscv_xlen == 64 STR(LWU) " %[insn], (%[addr])\n" #else STR(LW) " %[insn], (%[addr])\n" #endif - "csrw mstatus, %[mstatus]" + "csrw "STR(CSR_MSTATUS)", %[mstatus]" : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val) : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc)); #else ulong rvc_mask = 3, tmp; - asm ("csrrs %[mstatus], mstatus, %[mprv]\n" + asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n" "and %[tmp], %[addr], 2\n" "bnez %[tmp], 1f\n" #if __riscv_xlen == 64 @@ -107,7 +107,7 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus) "lhu %[tmp], 2(%[addr])\n" "sll %[tmp], %[tmp], 16\n" "add %[insn], %[insn], %[tmp]\n" - "2: csrw mstatus, %[mstatus]" + "2: csrw "STR(CSR_MSTATUS)", %[mstatus]" : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val), [tmp] "=&r" (tmp) : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (__riscv_xlen - 16)); |