diff options
| author | Anup Patel <anup.patel@wdc.com> | 2021-10-26 13:55:21 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-11-02 13:32:08 +0300 |
| commit | 013ba4ef3d94de67d040376535131012134ed54f (patch) | |
| tree | 215cb1ff0032b25bb1033f655146894f7492dd3e /include/sbi | |
| parent | c891acca172dfc60719419e19338508a83d97931 (diff) | |
| download | opensbi-013ba4ef3d94de67d040376535131012134ed54f.tar.xz | |
lib: sbi: Fix GPA passed to __sbi_hfence_gvma_xyz() functions
The parameter passed to HFENCE.GVMA instruction in rs1 register
is guest physical address right shifted by 2 (i.e. divided by 4).
Unfortunately, we overlooked the semantics of rs1 registers for
HFENCE.GVMA instruction and never right shifted guest physical
address by 2. This issue did not manifest for hypervisors till
now because all H-extension implementations (such as QEMU, Spike,
Rocket Core FPGA, etc) we tried till now were conservatively
flushing everything upon any HFENCE.GVMA instruction.
This patch fixes GPA passed to __sbi_hfence_gvma_vmid_gpa()
and __sbi_hfence_gvma_gpa() functions.
Fixes: 331ff6a162c1 ("lib: Support stage1 and stage2 tlb flushing")
Reported-by: Ian Huang <ihuang@ventanamicro.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Diffstat (limited to 'include/sbi')
| -rw-r--r-- | include/sbi/sbi_hfence.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/sbi/sbi_hfence.h b/include/sbi/sbi_hfence.h index 4420f27..d3958f1 100644 --- a/include/sbi/sbi_hfence.h +++ b/include/sbi/sbi_hfence.h @@ -12,13 +12,14 @@ #define __SBI_FENCE_H__ /** Invalidate Stage2 TLBs for given VMID and guest physical address */ -void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa, unsigned long vmid); +void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa_divby_4, + unsigned long vmid); /** Invalidate Stage2 TLBs for given VMID */ void __sbi_hfence_gvma_vmid(unsigned long vmid); /** Invalidate Stage2 TLBs for given guest physical address */ -void __sbi_hfence_gvma_gpa(unsigned long gpa); +void __sbi_hfence_gvma_gpa(unsigned long gpa_divby_4); /** Invalidate all possible Stage2 TLBs */ void __sbi_hfence_gvma_all(void); |