diff options
| author | Vivian Wang <dramforever@live.com> | 2022-08-04 17:32:27 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-08-22 06:19:29 +0300 |
| commit | 9529e360dfca40feeb2471bdde990207d44d68e1 (patch) | |
| tree | d247a378f4175a968c6a2cfa24a7bf3eba4125ba /include/sbi | |
| parent | a6a85579b6f4ad74b638b6d770143a7029cf8f57 (diff) | |
| download | opensbi-9529e360dfca40feeb2471bdde990207d44d68e1.tar.xz | |
include: Add mstatus[h].GVA encodings
The machine mode GVA field is in mstatus for RV64 and mstatush for RV32,
and is available if the hypervisor extension is available. If an
exception occurs, we may need to redirect the trap to HS-mode, in which
case, hstatus.GVA should be set to same as the machine mode GVA bit.
Add MSTATUS_GVA for RV64, MSTATUSH_GVA for RV32, and their SHIFT
encodings. The SHIFT index is helpful in assembly code, since field
extraction can be implemented in only one register. In pseudocode:
- For RV32: gva = (mstatus >> MSTATUS_GVA_SHIFT) & 1;
- For RV64: gva = (mstatush >> MSTATUSH_GVA_SHIFT) & 1;
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include/sbi')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 798afb7..8884301 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -38,10 +38,14 @@ #define MSTATUS_SXL _ULL(0x0000000C00000000) #define MSTATUS_SBE _ULL(0x0000001000000000) #define MSTATUS_MBE _ULL(0x0000002000000000) +#define MSTATUS_GVA _ULL(0x0000004000000000) +#define MSTATUS_GVA_SHIFT 38 #define MSTATUS_MPV _ULL(0x0000008000000000) #else #define MSTATUSH_SBE _UL(0x00000010) #define MSTATUSH_MBE _UL(0x00000020) +#define MSTATUSH_GVA _UL(0x00000040) +#define MSTATUSH_GVA_SHIFT 6 #define MSTATUSH_MPV _UL(0x00000080) #endif #define MSTATUS32_SD _UL(0x80000000) |