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author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-01-13 19:47:19 +0300 |
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committer | Anup Patel <anup@brainfault.org> | 2023-01-23 08:59:03 +0300 |
commit | dea0922f867f3d681ad3191fb562a082ea4a339f (patch) | |
tree | cce4b055c10a9f4eee4fd2276a32afdb5c9f4dcf /include/sbi_utils/fdt/fdt_fixup.h | |
parent | 230278dcf127e2a336d54748f03b5bc280656498 (diff) | |
download | opensbi-dea0922f867f3d681ad3191fb562a082ea4a339f.tar.xz |
platform: renesas/rzfive: Configure Local memory regions as part of root domain
Renesas RZ/Five RISC-V SoC has Instruction local memory and Data local
memory (ILM & DLM) mapped between region 0x30000 - 0x4FFFF. When a
virtual address falls within this range, the MMU doesn't trigger a page
fault; it assumes the virtual address is a physical address which can
cause undesired behaviours for statically linked applications/libraries.
To avoid this, add the ILM/DLM memory regions to the root domain region
of the PMPU with permissions set to 0x0 for S/U modes so that any access
to these regions gets blocked and for M-mode we grant full access (R/W/X).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include/sbi_utils/fdt/fdt_fixup.h')
0 files changed, 0 insertions, 0 deletions