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author | Vijai Kumar K <vijai@behindbytes.com> | 2020-06-17 16:55:16 +0300 |
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committer | Anup Patel <anup@brainfault.org> | 2020-06-19 06:51:46 +0300 |
commit | db56ef367cd6dc9dab94076f4c8a3fa9d91bd1f2 (patch) | |
tree | 1be9eab3dc74ee644be5cdfdbcf7ee42e3bc0908 /include/sbi_utils/serial | |
parent | 637b348224d557cd27c187d4465a90852ddde8a9 (diff) | |
download | opensbi-db56ef367cd6dc9dab94076f4c8a3fa9d91bd1f2.tar.xz |
platform: Add support for Shakti C-class SoC from IIT-M
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md
We add OpenSBI support for Shakti C-class SoC.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'include/sbi_utils/serial')
-rw-r--r-- | include/sbi_utils/serial/shakti-uart.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/sbi_utils/serial/shakti-uart.h b/include/sbi_utils/serial/shakti-uart.h new file mode 100644 index 0000000..08043be --- /dev/null +++ b/include/sbi_utils/serial/shakti-uart.h @@ -0,0 +1,18 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Vijai Kumar K <vijai@behindbytes.com> + */ + +#ifndef __SERIAL_SHAKTI_UART_H__ +#define __SERIAL_SHAKTI_UART_H__ + +#include <sbi/sbi_types.h> + +void shakti_uart_putc(char ch); + +int shakti_uart_getc(void); + +int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate); + +#endif |