diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-11-08 21:52:59 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-11-11 15:15:12 +0300 |
| commit | 9134c3643e420b1917cf98940552ef16467f7a34 (patch) | |
| tree | a744935898916dd4b71c2c49fb0f7e0cc1508550 /include | |
| parent | 867c65360df283f056afa963ad8333e9c1eb21bb (diff) | |
| download | opensbi-9134c3643e420b1917cf98940552ef16467f7a34.tar.xz | |
lib: sbi: Delegate PMU counter overflow interrupt to S mode
OpenSBI doesn't handle PMU counters for now.
Delegate the overflow counter to S-mode always.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 14caa95..ca63435 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -86,6 +86,7 @@ #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 #define MIP_SSIP (_UL(1) << IRQ_S_SOFT) #define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT) @@ -97,6 +98,7 @@ #define MIP_VSEIP (_UL(1) << IRQ_VS_EXT) #define MIP_MEIP (_UL(1) << IRQ_M_EXT) #define MIP_SGEIP (_UL(1) << IRQ_S_GEXT) +#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP |