diff options
| author | Anup Patel <anup.patel@wdc.com> | 2019-12-12 20:35:03 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-12-16 12:18:12 +0300 |
| commit | bd732ae612407a05c3394bc19ede98013b0b35d5 (patch) | |
| tree | e8ae8204d5c1504b08be01911719b9e6e832c62d /include | |
| parent | dc40042322fecd0c3eec90fcf4528f211ee2fa58 (diff) | |
| download | opensbi-bd732ae612407a05c3394bc19ede98013b0b35d5.tar.xz | |
include: Add guest external interrupt related defines
With RISC-V H-extension v0.5 draft, we have special support for guest
external interrupts so this patch adds related defines which were
missed-out previously.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 316d743..6dd0d30 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -78,6 +78,7 @@ #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 #define MIP_SSIP (_UL(1) << IRQ_S_SOFT) #define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT) @@ -88,6 +89,7 @@ #define MIP_SEIP (_UL(1) << IRQ_S_EXT) #define MIP_VSEIP (_UL(1) << IRQ_VS_EXT) #define MIP_MEIP (_UL(1) << IRQ_M_EXT) +#define MIP_SGEIP (_UL(1) << IRQ_S_GEXT) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP @@ -213,10 +215,12 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 #define CSR_HCOUNTERNEN 0x606 +#define CSR_HGEIE 0x607 #define CSR_HTVAL 0x643 #define CSR_HIP 0x644 #define CSR_HTINST 0x64a #define CSR_HGATP 0x680 +#define CSR_HGEIP 0xe07 #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 |