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| author | Anup Patel <anup.patel@wdc.com> | 2020-05-28 06:07:42 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-06-08 13:11:23 +0300 |
| commit | 1b8c0128f1d79d69ea0a46b758fef4be8dc0a73e (patch) | |
| tree | f7f5a322710d6cd9638444b1130b1662c883f459 /include | |
| parent | 51f0e4a0533fe8b5d713379ab3a6cb676add82da (diff) | |
| download | opensbi-1b8c0128f1d79d69ea0a46b758fef4be8dc0a73e.tar.xz | |
lib: Add RISC-V hypervisor v0.6.1 support
To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index fd96b0f..827c86c 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -61,12 +61,20 @@ #define SSTATUS64_UXL MSTATUS_UXL #define SSTATUS64_SD MSTATUS64_SD +#if __riscv_xlen == 64 +#define HSTATUS_VSXL _UL(0x300000000) +#define HSTATUS_VSXL_SHIFT 32 +#endif #define HSTATUS_VTSR _UL(0x00400000) +#define HSTATUS_VTW _UL(0x00200000) #define HSTATUS_VTVM _UL(0x00100000) -#define HSTATUS_SP2V _UL(0x00000200) -#define HSTATUS_SP2P _UL(0x00000100) +#define HSTATUS_VGEIN _UL(0x0003f000) +#define HSTATUS_VGEIN_SHIFT 12 +#define HSTATUS_HU _UL(0x00000200) +#define HSTATUS_SPVP _UL(0x00000100) #define HSTATUS_SPV _UL(0x00000080) -#define HSTATUS_SPRV _UL(0x00000001) +#define HSTATUS_GVA _UL(0x00000040) +#define HSTATUS_VSBE _UL(0x00000020) #define IRQ_S_SOFT 1 #define IRQ_VS_SOFT 2 @@ -424,6 +432,7 @@ #define CAUSE_STORE_PAGE_FAULT 0xf #define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 #define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 #define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 #define INSN_MATCH_LB 0x3 |