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| author | Atish Patra <atishp@rivosinc.com> | 2022-04-28 21:48:29 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-05-07 07:10:59 +0300 |
| commit | b0c9df514bdb29a0c90c9868f4209f2ac7a6d567 (patch) | |
| tree | 2c50a6f083dfdbc8b54b5b01125ac73ac7023154 /lib/sbi/riscv_asm.c | |
| parent | e576b3e620675b48a34cc2e9c6a589df3ceaf4cf (diff) | |
| download | opensbi-b0c9df514bdb29a0c90c9868f4209f2ac7a6d567.tar.xz | |
lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmf
MHPMEVENT3H-31H are defined in sscofpmf extension. Thus, they should be
accessed only if sscofpmf is present.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/sbi/riscv_asm.c')
| -rw-r--r-- | lib/sbi/riscv_asm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 5eab1ed..ddc4c13 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -139,6 +139,10 @@ unsigned long csr_read_num(int csr_num) switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret) switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret) switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret) + /** + * The CSR range MHPMEVENT[3-16]H are available only if sscofpmf + * extension is present. The caller must ensure that. + */ switchcase_csr_read(CSR_MHPMEVENT3H, ret) switchcase_csr_read_4(CSR_MHPMEVENT4H, ret) switchcase_csr_read_8(CSR_MHPMEVENT8H, ret) |