summaryrefslogtreecommitdiff
path: root/lib/sbi/sbi_ecall_pmu.c
diff options
context:
space:
mode:
authorAtish Patra <atish.patra@wdc.com>2021-07-10 19:18:13 +0300
committerAnup Patel <anup@brainfault.org>2021-07-11 08:08:02 +0300
commit37f9b0f2f265b2f312d974fb8d100b85b3faf94f (patch)
tree914b0a37f87f7fe6a8bee2f248019bfa15012055 /lib/sbi/sbi_ecall_pmu.c
parentae72ec091508196e29c07ae46bca106373d31e39 (diff)
downloadopensbi-37f9b0f2f265b2f312d974fb8d100b85b3faf94f.tar.xz
lib: sbi: Implement SBI PMU extension
RISC-V SBI specfication 0.3 defines a PMU extension that allows supervisor mode to start/stop/configure pmu related events. This patch implements all of the functionality defined in the specification. Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_ecall_pmu.c')
-rw-r--r--lib/sbi/sbi_ecall_pmu.c93
1 files changed, 93 insertions, 0 deletions
diff --git a/lib/sbi/sbi_ecall_pmu.c b/lib/sbi/sbi_ecall_pmu.c
new file mode 100644
index 0000000..39d3857
--- /dev/null
+++ b/lib/sbi/sbi_ecall_pmu.c
@@ -0,0 +1,93 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_version.h>
+#include <sbi/sbi_pmu.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/riscv_asm.h>
+
+static int sbi_ecall_pmu_handler(unsigned long extid, unsigned long funcid,
+ const struct sbi_trap_regs *regs,
+ unsigned long *out_val,
+ struct sbi_trap_info *out_trap)
+{
+ int ret = 0;
+ uint64_t temp;
+
+ switch (funcid) {
+ case SBI_EXT_PMU_NUM_COUNTERS:
+ ret = sbi_pmu_num_ctr();
+ if (ret >= 0) {
+ *out_val = ret;
+ ret = 0;
+ }
+ break;
+ case SBI_EXT_PMU_COUNTER_GET_INFO:
+ ret = sbi_pmu_ctr_get_info(regs->a0, out_val);
+ break;
+ case SBI_EXT_PMU_COUNTER_CFG_MATCH:
+#if __riscv_xlen == 32
+ temp = ((uint64_t)regs->a5 << 32) | regs->a4;
+#else
+ temp = regs->a4;
+#endif
+ ret = sbi_pmu_ctr_cfg_match(regs->a0, regs->a1, regs->a2,
+ regs->a3, temp);
+ if (ret >= 0) {
+ *out_val = ret;
+ ret = 0;
+ }
+
+ break;
+ case SBI_EXT_PMU_COUNTER_FW_READ:
+ ret = sbi_pmu_ctr_read(regs->a0, out_val);
+ break;
+ case SBI_EXT_PMU_COUNTER_START:
+
+#if __riscv_xlen == 32
+ temp = ((uint64_t)regs->a4 << 32) | regs->a3;
+#else
+ temp = regs->a3;
+#endif
+ ret = sbi_pmu_ctr_start(regs->a0, regs->a1, regs->a2, temp);
+ break;
+ case SBI_EXT_PMU_COUNTER_STOP:
+ ret = sbi_pmu_ctr_stop(regs->a0, regs->a1, regs->a2);
+ break;
+ default:
+ ret = SBI_ENOTSUPP;
+ };
+
+ return ret;
+}
+
+static int sbi_ecall_pmu_probe(unsigned long extid, unsigned long *out_val)
+{
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+ /* SBI PMU extension is useless without mcount inhibit features */
+ if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT))
+ *out_val = 1;
+ else
+ *out_val = 0;
+
+ return 0;
+}
+
+struct sbi_ecall_extension ecall_pmu = {
+ .extid_start = SBI_EXT_PMU,
+ .extid_end = SBI_EXT_PMU,
+ .handle = sbi_ecall_pmu_handler,
+ .probe = sbi_ecall_pmu_probe,
+};