diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-07-10 19:18:14 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-07-11 08:08:23 +0300 |
| commit | 764a17d852a8cc80050016a6e2ccdcaddd43f68c (patch) | |
| tree | 03db9a920bfd843301af4c7eecac02bb76921eb1 /lib/sbi/sbi_misaligned_ldst.c | |
| parent | 37f9b0f2f265b2f312d974fb8d100b85b3faf94f (diff) | |
| download | opensbi-764a17d852a8cc80050016a6e2ccdcaddd43f68c.tar.xz | |
lib: sbi: Implement firmware counters
RISC-V SBI v0.3 specification defines a set of firmware events that can
provide additional information about the current firmware context. All
of the firmware event monitoring are enabled now. The firmware
events must be defined as raw perf event with MSB set as specified in the
specification.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 5057cb5..c879ce7 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -12,6 +12,7 @@ #include <sbi/riscv_fp.h> #include <sbi/sbi_error.h> #include <sbi/sbi_misaligned_ldst.h> +#include <sbi/sbi_pmu.h> #include <sbi/sbi_trap.h> #include <sbi/sbi_unpriv.h> @@ -29,6 +30,8 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, struct sbi_trap_info uptrap; int i, fp = 0, shift = 0, len = 0; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_LOAD); + if (tinst & 0x1) { /* * Bit[0] == 1 implies trapped instruction value is @@ -149,6 +152,8 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, struct sbi_trap_info uptrap; int i, len = 0; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_STORE); + if (tinst & 0x1) { /* * Bit[0] == 1 implies trapped instruction value is |