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| author | Damien Le Moal <damien.lemoal@wdc.com> | 2020-03-12 08:20:37 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-03-13 07:32:42 +0300 |
| commit | 86d37bbd7ddf44430eb63ac521261f2fa11733b0 (patch) | |
| tree | 8912ecbec6ec3bf2aba67c11c1fdbab8180c6dfb /lib/sbi/sbi_misaligned_ldst.c | |
| parent | 757bb44e6eff4f093bcc8b38333db2a37ffe47a4 (diff) | |
| download | opensbi-86d37bbd7ddf44430eb63ac521261f2fa11733b0.tar.xz | |
lib: sbi: Fix misaligned trap handling
Compile time checks of __riscv_compressed can only check if OpenSBI is
being compiled using compressed instructions or not. Checking this macro
does not indicate if an instruction that generated a misaligned trap is
a compressed instruction or not.
Since the misaligned trap handling code inspects instructions _C_ bits
to detect compressed instructions, we can remove all static checks on
__riscv_compressed and dissociate hanlding of misaligned traps and
OpenSBI compilation.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 400372c..b59efa0 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -72,7 +72,6 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, shift = 8 * (sizeof(ulong) - len); } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) { len = 2; -#ifdef __riscv_compressed #if __riscv_xlen >= 64 } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) { len = 8; @@ -109,7 +108,6 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, len = 4; #endif #endif -#endif } else { uptrap.epc = regs->mepc; uptrap.cause = mcause; @@ -189,7 +187,6 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, #endif } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { len = 2; -#ifdef __riscv_compressed #if __riscv_xlen >= 64 } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) { len = 8; @@ -222,7 +219,6 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, val.data_ulong = GET_F32_RS2C(insn, regs); #endif #endif -#endif } else { uptrap.epc = regs->mepc; uptrap.cause = mcause; |