diff options
| author | Anup Patel <anup.patel@wdc.com> | 2019-11-16 14:08:53 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-11-21 11:26:03 +0300 |
| commit | b1d8c988bcca84cf7cd8ee5bf4fe528e256cfeab (patch) | |
| tree | 26bea8e8703474f9b741e8b9d7acc0c7f91a568a /lib/sbi/sbi_misaligned_ldst.c | |
| parent | 838657c0524f148d8aaec8225cd0ab9e2e2c7303 (diff) | |
| download | opensbi-b1d8c988bcca84cf7cd8ee5bf4fe528e256cfeab.tar.xz | |
lib: No need to set VSSTATUS.MXR bit in get_insn()
We don't need to set VSSTATUS.MXR bit in get_insn() for
unpriv instruction read because MSTATUS.MXR bit applies
to both "Stage1" and "Stage2" page tables.
This also allows us to remove the "virt" parameter of
get_insn() function.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'lib/sbi/sbi_misaligned_ldst.c')
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 10c467c..a41b908 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -29,12 +29,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, struct unpriv_trap uptrap; ulong addr = csr_read(CSR_MTVAL); int i, fp = 0, shift = 0, len = 0; -#if __riscv_xlen == 32 - bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE; -#else - bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE; -#endif - ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap); + ulong insn = get_insn(regs->mepc, scratch, &uptrap); if (uptrap.cause) return sbi_trap_redirect(regs, scratch, regs->mepc, @@ -136,12 +131,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, struct unpriv_trap uptrap; ulong addr = csr_read(CSR_MTVAL); int i, len = 0; -#if __riscv_xlen == 32 - bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE; -#else - bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE; -#endif - ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap); + ulong insn = get_insn(regs->mepc, scratch, &uptrap); if (uptrap.cause) return sbi_trap_redirect(regs, scratch, regs->mepc, |