diff options
| author | Vivian Wang <dramforever@live.com> | 2022-08-04 17:32:28 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-08-22 06:19:39 +0300 |
| commit | 1fbe7778c9843930ce3dadb35804d56e1f782479 (patch) | |
| tree | 2d33940f766a9d0da22b67d0b90a28a5424733b0 /lib/sbi | |
| parent | 9529e360dfca40feeb2471bdde990207d44d68e1 (diff) | |
| download | opensbi-1fbe7778c9843930ce3dadb35804d56e1f782479.tar.xz | |
lib: sbi_trap: Save mstatus[h].GVA in trap->gva
The machine mode GVA field is available if the hypervisor extension is
implemented, and indicates if mtval is a guest virtual address. Add a
gva field to sbi_trap_info for this, and in __sbi_expected_trap_hext,
save mstatus[h].GVA to it, so that gva indicates if tval is a guest
virtual address. If the hypervisor extension is not implemented, always
set gva to 0.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/sbi')
| -rw-r--r-- | lib/sbi/sbi_expected_trap.S | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/lib/sbi/sbi_expected_trap.S b/lib/sbi/sbi_expected_trap.S index 24891c7..a5ef26a 100644 --- a/lib/sbi/sbi_expected_trap.S +++ b/lib/sbi/sbi_expected_trap.S @@ -22,7 +22,7 @@ .align 3 .global __sbi_expected_trap __sbi_expected_trap: - /* Without H-extension so, MTVAL2 and MTINST CSRs not available */ + /* Without H-extension so, MTVAL2 and MTINST CSRs and GVA not available */ csrr a4, CSR_MEPC REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3) csrr a4, CSR_MCAUSE @@ -31,6 +31,7 @@ __sbi_expected_trap: REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3) REG_S zero, SBI_TRAP_INFO_OFFSET(tval2)(a3) REG_S zero, SBI_TRAP_INFO_OFFSET(tinst)(a3) + REG_S zero, SBI_TRAP_INFO_OFFSET(gva)(a3) csrr a4, CSR_MEPC addi a4, a4, 4 csrw CSR_MEPC, a4 @@ -39,7 +40,7 @@ __sbi_expected_trap: .align 3 .global __sbi_expected_trap_hext __sbi_expected_trap_hext: - /* With H-extension so, MTVAL2 and MTINST CSRs available */ + /* With H-extension so, MTVAL2 and MTINST CSRs and GVA available */ csrr a4, CSR_MEPC REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3) csrr a4, CSR_MCAUSE @@ -50,6 +51,18 @@ __sbi_expected_trap_hext: REG_S a4, SBI_TRAP_INFO_OFFSET(tval2)(a3) csrr a4, CSR_MTINST REG_S a4, SBI_TRAP_INFO_OFFSET(tinst)(a3) + + /* Extract GVA bit from MSTATUS or MSTATUSH */ +#if __riscv_xlen == 32 + csrr a4, CSR_MSTATUSH + srli a4, a4, MSTATUSH_GVA_SHIFT +#else + csrr a4, CSR_MSTATUS + srli a4, a4, MSTATUS_GVA_SHIFT +#endif + andi a4, a4, 1 + REG_S a4, SBI_TRAP_INFO_OFFSET(gva)(a3) + csrr a4, CSR_MEPC addi a4, a4, 4 csrw CSR_MEPC, a4 |