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| author | Samuel Holland <samuel@sholland.org> | 2021-10-20 04:58:38 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-06-21 06:50:59 +0300 |
| commit | 7738345396fbbae543a5af14fbc965d9163c12a0 (patch) | |
| tree | 134b49530b8d6cb4cf928384fd8f960eff9d50ad /lib/utils/irqchip/plic.c | |
| parent | c6530012d46ed9c9655c426450bfa3aabcc0eadd (diff) | |
| download | opensbi-7738345396fbbae543a5af14fbc965d9163c12a0.tar.xz | |
lib: utils/timer: Add a separate compatible for the D1 CLINT
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit
MMIO access. A property was added to support this quirk (and that
property was copied to the ACLINT MTIMER code). However, since this
difference in behavior makes the D1 CLINT incompatible with the SiFive
CLINT's programming interface, a better solution is to use a separate
compatible string.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/irqchip/plic.c')
0 files changed, 0 insertions, 0 deletions