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| author | Atish Patra <atish.patra@wdc.com> | 2020-04-03 21:13:08 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-04-06 06:28:56 +0300 |
| commit | f281de885ec9417a6d3ae702d0ed5acab6396bee (patch) | |
| tree | c67743b7504f94e18ce5c4efb3a84a9383a7dfa0 /lib/utils/irqchip | |
| parent | e5a7f556ce22984128bed0a336551a968c818450 (diff) | |
| download | opensbi-f281de885ec9417a6d3ae702d0ed5acab6396bee.tar.xz | |
lib: irqchip/plic: Fix maximum priority threshold value
As per the PLIC specification, maximum priority threshold value is 0x7.
Even though, writing a higher value doesn't cause any error in qemu
hifive unleashed, there may be some implementation which checks the upper
and may result in an illegal access.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'lib/utils/irqchip')
| -rw-r--r-- | lib/utils/irqchip/plic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index 40c4170..7c40d28 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -66,11 +66,11 @@ int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id) /* By default, disable M-mode threshold */ if (m_cntx_id > -1) - plic_set_thresh(m_cntx_id, 0xffffffff); + plic_set_thresh(m_cntx_id, 0x7); /* By default, disable S-mode threshold */ if (s_cntx_id > -1) - plic_set_thresh(s_cntx_id, 0xffffffff); + plic_set_thresh(s_cntx_id, 0x7); return 0; } |