diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2023-01-20 06:05:11 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-01-22 15:03:03 +0300 |
| commit | 787296ae92b7ec5363dab71b6d036e8def31c6f7 (patch) | |
| tree | d7d13ea7fda379ea99cc72cf4b52c95447c91a15 /platform/generic/include/andes/andes45.h | |
| parent | 9c4eb3521e515603671198295f2c7d5114e4c601 (diff) | |
| download | opensbi-787296ae92b7ec5363dab71b6d036e8def31c6f7.tar.xz | |
platform: andes/ae350: Implement hart hotplug using HSM extension
Add hart_start() and hart_stop() callbacks for the multi-core ae350
platform, it utilizes the ATCSMU to put the harts into power-gated
deep sleep mode. The programming sequence is stated as below:
1. Set the wakeup events to PCSm_WE
2. Set the sleep command to PCSm_CTL
3. Set the reset vector to HARTm_RESET_VECTOR_{LO|HI}
4. Write back and invalidate D-cache by executing the CCTL command L1D_WBINVAL_ALL
5. Disable I/D-cache by clearing mcache_ctl.{I|D}C_EN
6. Disable D-cache coherency by clearing mcache_ctl_.DC_COHEN
7. Wait for mcache_ctl.DC_COHSTA to be cleared to ensure the previous step is completed
8. Execute WFI
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform/generic/include/andes/andes45.h')
| -rw-r--r-- | platform/generic/include/andes/andes45.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h new file mode 100644 index 0000000..08b3d18 --- /dev/null +++ b/platform/generic/include/andes/andes45.h @@ -0,0 +1,10 @@ +#ifndef _RISCV_ANDES45_H +#define _RISCV_ANDES45_H + +#define CSR_MARCHID_MICROID 0xfff + +/* Memory and Miscellaneous Registers */ +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MCCTLCOMMAND 0x7cc + +#endif /* _RISCV_ANDES45_H */ |