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| author | Damien Le Moal <damien.lemoal@wdc.com> | 2018-12-21 11:20:56 +0300 |
|---|---|---|
| committer | Damien Le Moal <damien.lemoal@wdc.com> | 2018-12-21 11:20:56 +0300 |
| commit | 07ee5f2e328b7ee3ed57b51f98f2765ae1701a99 (patch) | |
| tree | 5b105c3825f6b747bdb25924b398bcc4168f0d4a /platform/kendryte/k210/platform.h | |
| parent | 5563a0335421c3e1d69dc62a1b58675ddf3d1e5b (diff) | |
| download | opensbi-07ee5f2e328b7ee3ed57b51f98f2765ae1701a99.tar.xz | |
Kendryte-k210: Remove unnecessary asm functions
Use functions defined in sbi/riscv_asm.h.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Diffstat (limited to 'platform/kendryte/k210/platform.h')
| -rw-r--r-- | platform/kendryte/k210/platform.h | 37 |
1 files changed, 3 insertions, 34 deletions
diff --git a/platform/kendryte/k210/platform.h b/platform/kendryte/k210/platform.h index 14a4bbd..6b520cf 100644 --- a/platform/kendryte/k210/platform.h +++ b/platform/kendryte/k210/platform.h @@ -16,6 +16,8 @@ #ifndef _PLATFORM_H_ #define _PLATFORM_H_ +#include <sbi/riscv_asm.h> + /* Register base address */ /* Under Coreplex */ @@ -83,40 +85,7 @@ #define SPI1_BASE_ADDR (0x53000000U) #define SPI3_BASE_ADDR (0x54000000U) -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define read_time() read_csr(mtime) -#define read_cycle() read_csr(mcycle) -#define current_coreid() read_csr(mhartid) +#define read_cycle() csr_read(mcycle) /* * PLIC External Interrupt Numbers |