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authorAnup Patel <anup.patel@wdc.com>2018-12-21 08:05:04 +0300
committerAnup Patel <anup@brainfault.org>2018-12-21 08:05:04 +0300
commit089f70a1798b5c631e87eeb26b7eb2593571c63d (patch)
tree921799751ffa8296e19ca34eff589daa2fd38d8e /platform/qemu/virt/platform.c
parent6f02b6938f8e607d38ee8de5a59581d554af0d3f (diff)
downloadopensbi-089f70a1798b5c631e87eeb26b7eb2593571c63d.tar.xz
top: Rename "plat" to "platform" everywhere
This patch renames "plat" to "platform" everywhere for better readablility. Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'platform/qemu/virt/platform.c')
-rw-r--r--platform/qemu/virt/platform.c112
1 files changed, 112 insertions, 0 deletions
diff --git a/platform/qemu/virt/platform.c b/platform/qemu/virt/platform.c
new file mode 100644
index 0000000..e59cdfd
--- /dev/null
+++ b/platform/qemu/virt/platform.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_platform.h>
+#include <plat/irqchip/plic.h>
+#include <plat/serial/uart8250.h>
+#include <plat/sys/clint.h>
+
+#define VIRT_TEST_ADDR 0x100000
+
+#define VIRT_CLINT_ADDR 0x2000000
+
+#define VIRT_PLIC_ADDR 0xc000000
+#define VIRT_PLIC_NUM_SOURCES 127
+#define VIRT_PLIC_NUM_PRIORITIES 7
+
+#define VIRT_UART16550_ADDR 0x10000000
+
+static int virt_cold_final_init(void)
+{
+ return plic_fdt_fixup(sbi_scratch_thishart_arg1_ptr(), "riscv,plic0");
+}
+
+static u32 virt_pmp_region_count(u32 target_hart)
+{
+ return 1;
+}
+
+static int virt_pmp_region_info(u32 target_hart, u32 index,
+ ulong *prot, ulong *addr, ulong *log2size)
+{
+ int ret = 0;
+
+ switch (index) {
+ case 0:
+ *prot = PMP_R | PMP_W | PMP_X;
+ *addr = 0;
+ *log2size = __riscv_xlen;
+ break;
+ default:
+ ret = -1;
+ break;
+ };
+
+ return ret;
+}
+
+static int virt_console_init(void)
+{
+ return uart8250_init(VIRT_UART16550_ADDR,
+ 1843200, 115200, 0, 1);
+}
+
+static int virt_cold_irqchip_init(void)
+{
+ return plic_cold_irqchip_init(VIRT_PLIC_ADDR,
+ VIRT_PLIC_NUM_SOURCES,
+ PLAT_HART_COUNT);
+}
+
+static int virt_cold_ipi_init(void)
+{
+ return clint_cold_ipi_init(VIRT_CLINT_ADDR,
+ PLAT_HART_COUNT);
+}
+
+static int virt_cold_timer_init(void)
+{
+ return clint_cold_timer_init(VIRT_CLINT_ADDR,
+ PLAT_HART_COUNT);
+}
+
+static int virt_system_down(u32 type)
+{
+ /* For now nothing to do. */
+ return 0;
+}
+
+struct sbi_platform platform = {
+ .name = STRINGIFY(PLAT_NAME),
+ .features = SBI_PLATFORM_HAS_MMIO_TIMER_VALUE,
+ .hart_count = PLAT_HART_COUNT,
+ .hart_stack_size = PLAT_HART_STACK_SIZE,
+ .pmp_region_count = virt_pmp_region_count,
+ .pmp_region_info = virt_pmp_region_info,
+ .cold_final_init = virt_cold_final_init,
+ .console_putc = uart8250_putc,
+ .console_getc = uart8250_getc,
+ .console_init = virt_console_init,
+ .cold_irqchip_init = virt_cold_irqchip_init,
+ .warm_irqchip_init = plic_warm_irqchip_init,
+ .ipi_inject = clint_ipi_inject,
+ .ipi_sync = clint_ipi_sync,
+ .ipi_clear = clint_ipi_clear,
+ .warm_ipi_init = clint_warm_ipi_init,
+ .cold_ipi_init = virt_cold_ipi_init,
+ .timer_value = clint_timer_value,
+ .timer_event_stop = clint_timer_event_stop,
+ .timer_event_start = clint_timer_event_start,
+ .warm_timer_init = clint_warm_timer_init,
+ .cold_timer_init = virt_cold_timer_init,
+ .system_reboot = virt_system_down,
+ .system_shutdown = virt_system_down
+};