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| author | Liu Yibin <yibin_liu@c-sky.com> | 2020-01-13 06:20:56 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-01-15 03:16:38 +0300 |
| commit | 7daccaeebd44a0e4ad4a24884ae819787a953116 (patch) | |
| tree | 02f4f12a69386f14a8db7714c26c63df67622f9a /platform/thead/c910 | |
| parent | 6ffe1bed09be1cb2db8755b30c0258849184400b (diff) | |
| download | opensbi-7daccaeebd44a0e4ad4a24884ae819787a953116.tar.xz | |
platform: thead/c910: Don't enable L2 cache in warm boot
Since all harts share the same L2 cache now, there's
no need to Enable L2 cache in warm boot.
Signed-off-by: Liu Yibin <yibin_liu@c-sky.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'platform/thead/c910')
| -rw-r--r-- | platform/thead/c910/platform.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/platform/thead/c910/platform.c b/platform/thead/c910/platform.c index 1ad3e49..83cfc9d 100644 --- a/platform/thead/c910/platform.c +++ b/platform/thead/c910/platform.c @@ -48,7 +48,6 @@ static int c910_early_init(bool cold_boot) csr_write(CSR_MCOR, c910_regs.mcor); csr_write(CSR_MHCR, c910_regs.mhcr); - csr_write(CSR_MCCR2, c910_regs.mccr2); csr_write(CSR_MHINT, c910_regs.mhint); csr_write(CSR_MXSTATUS, c910_regs.mxstatus); } |