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| author | Liu Yibin <yibin_liu@c-sky.com> | 2020-01-13 06:20:57 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-01-15 03:18:44 +0300 |
| commit | a73d45ccac1794afba111dd1b46d3b7912cfe019 (patch) | |
| tree | 414f790a836d23c2100ebc291b76040f0192a362 /platform/thead | |
| parent | 7daccaeebd44a0e4ad4a24884ae819787a953116 (diff) | |
| download | opensbi-a73d45ccac1794afba111dd1b46d3b7912cfe019.tar.xz | |
platform: thead/c910: Don't set plic/clint address in warm boot
Since all harts share the same plic/clint address now, setting
them during cold boot is just fine.
Signed-off-by: Liu Yibin <yibin_liu@c-sky.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'platform/thead')
| -rw-r--r-- | platform/thead/c910/platform.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/platform/thead/c910/platform.c b/platform/thead/c910/platform.c index 83cfc9d..9d73bf4 100644 --- a/platform/thead/c910/platform.c +++ b/platform/thead/c910/platform.c @@ -34,6 +34,10 @@ static int c910_early_init(bool cold_boot) c910_regs.mccr2 = csr_read(CSR_MCCR2); c910_regs.mhint = csr_read(CSR_MHINT); c910_regs.mxstatus = csr_read(CSR_MXSTATUS); + + c910_regs.plic_base_addr = csr_read(CSR_PLIC_BASE); + c910_regs.clint_base_addr = + c910_regs.plic_base_addr + C910_PLIC_CLINT_OFFSET; } else { /* Store to other core */ csr_write(CSR_PMPADDR0, c910_regs.pmpaddr0); @@ -52,10 +56,6 @@ static int c910_early_init(bool cold_boot) csr_write(CSR_MXSTATUS, c910_regs.mxstatus); } - c910_regs.plic_base_addr = csr_read(CSR_PLIC_BASE); - c910_regs.clint_base_addr = - c910_regs.plic_base_addr + C910_PLIC_CLINT_OFFSET; - return 0; } |