diff options
| author | Zong Li <zong.li@sifive.com> | 2022-04-15 05:24:20 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-04-17 11:27:48 +0300 |
| commit | 5c5cbb53a4fd2f7d2a7038b584f8ee01266cef04 (patch) | |
| tree | 6b5b44ba31b880503dc722bd2a707b0d8b14e1f4 /platform | |
| parent | 3383d6a4d1461bb029b21fa53417382e34ae4906 (diff) | |
| download | opensbi-5c5cbb53a4fd2f7d2a7038b584f8ee01266cef04.tar.xz | |
lib: utils/serial: support 'reg-offset' property
reg-offset property is used for offset to apply to the mapbase
from the start of the registers in 8250 UART. In Linux kernel,
it has been handled in 8250 UART driver.
dt-bindings:
<linux>/Documentation/devicetree/bindings/serial/8250.yaml
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform')
| -rw-r--r-- | platform/andes/ae350/platform.c | 3 | ||||
| -rw-r--r-- | platform/andes/ae350/platform.h | 1 | ||||
| -rw-r--r-- | platform/fpga/ariane/platform.c | 4 | ||||
| -rw-r--r-- | platform/fpga/openpiton/platform.c | 4 | ||||
| -rw-r--r-- | platform/template/platform.c | 2 |
5 files changed, 10 insertions, 4 deletions
diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c index 01232d0..6bd0a69 100644 --- a/platform/andes/ae350/platform.c +++ b/platform/andes/ae350/platform.c @@ -69,7 +69,8 @@ static int ae350_console_init(void) AE350_UART_FREQUENCY, AE350_UART_BAUDRATE, AE350_UART_REG_SHIFT, - AE350_UART_REG_WIDTH); + AE350_UART_REG_WIDTH, + AE350_UART_REG_OFFSET); } /* Initialize the platform interrupt controller for current HART. */ diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h index f34ca0f..9b54816 100644 --- a/platform/andes/ae350/platform.h +++ b/platform/andes/ae350/platform.h @@ -28,6 +28,7 @@ #define AE350_UART_BAUDRATE 38400 #define AE350_UART_REG_SHIFT 2 #define AE350_UART_REG_WIDTH 0 +#define AE350_UART_REG_OFFSET 0 /*Memory and Miscellaneous Registers*/ #define CSR_MILMB 0x7c0 diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index c6f0ffd..3fdc03b 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -23,6 +23,7 @@ #define ARIANE_UART_BAUDRATE 115200 #define ARIANE_UART_REG_SHIFT 2 #define ARIANE_UART_REG_WIDTH 4 +#define ARIANE_UART_REG_OFFSET 0 #define ARIANE_PLIC_ADDR 0xc000000 #define ARIANE_PLIC_NUM_SOURCES 3 #define ARIANE_HART_COUNT 1 @@ -92,7 +93,8 @@ static int ariane_console_init(void) ARIANE_UART_FREQ, ARIANE_UART_BAUDRATE, ARIANE_UART_REG_SHIFT, - ARIANE_UART_REG_WIDTH); + ARIANE_UART_REG_WIDTH, + ARIANE_UART_REG_OFFSET); } static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id) diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index 59c6702..15e289a 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -22,6 +22,7 @@ #define OPENPITON_DEFAULT_UART_BAUDRATE 115200 #define OPENPITON_DEFAULT_UART_REG_SHIFT 0 #define OPENPITON_DEFAULT_UART_REG_WIDTH 1 +#define OPENPITON_DEFAULT_UART_REG_OFFSET 0 #define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000 #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2 #define OPENPITON_DEFAULT_HART_COUNT 3 @@ -127,7 +128,8 @@ static int openpiton_console_init(void) uart.freq, uart.baud, OPENPITON_DEFAULT_UART_REG_SHIFT, - OPENPITON_DEFAULT_UART_REG_WIDTH); + OPENPITON_DEFAULT_UART_REG_WIDTH, + OPENPITON_DEFAULT_UART_REG_OFFSET); } static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id) diff --git a/platform/template/platform.c b/platform/template/platform.c index d6806e6..5524847 100644 --- a/platform/template/platform.c +++ b/platform/template/platform.c @@ -79,7 +79,7 @@ static int platform_console_init(void) { /* Example if the generic UART8250 driver is used */ return uart8250_init(PLATFORM_UART_ADDR, PLATFORM_UART_INPUT_FREQ, - PLATFORM_UART_BAUDRATE, 0, 1); + PLATFORM_UART_BAUDRATE, 0, 1, 0); } /* |