diff options
| -rw-r--r-- | include/sbi/sbi_misaligned_ldst.h | 13 | ||||
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 16 | ||||
| -rw-r--r-- | lib/sbi/sbi_trap.c | 8 |
3 files changed, 12 insertions, 25 deletions
diff --git a/include/sbi/sbi_misaligned_ldst.h b/include/sbi/sbi_misaligned_ldst.h index d95c845..ab27eb4 100644 --- a/include/sbi/sbi_misaligned_ldst.h +++ b/include/sbi/sbi_misaligned_ldst.h @@ -13,16 +13,11 @@ #include <sbi/sbi_types.h> struct sbi_trap_regs; -struct sbi_scratch; -int sbi_misaligned_load_handler(u32 hartid, ulong mcause, - ulong addr, ulong tval2, ulong tinst, - struct sbi_trap_regs *regs, - struct sbi_scratch *scratch); +int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, + struct sbi_trap_regs *regs); -int sbi_misaligned_store_handler(u32 hartid, ulong mcause, - ulong addr, ulong tval2, ulong tinst, - struct sbi_trap_regs *regs, - struct sbi_scratch *scratch); +int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, + struct sbi_trap_regs *regs); #endif diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 7c15a40..29d79bb 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -21,10 +21,8 @@ union reg_data { u64 data_u64; }; -int sbi_misaligned_load_handler(u32 hartid, ulong mcause, - ulong addr, ulong tval2, ulong tinst, - struct sbi_trap_regs *regs, - struct sbi_scratch *scratch) +int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, + struct sbi_trap_regs *regs) { ulong insn; union reg_data val; @@ -110,7 +108,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, #endif } else { uptrap.epc = regs->mepc; - uptrap.cause = mcause; + uptrap.cause = CAUSE_MISALIGNED_LOAD; uptrap.tval = addr; uptrap.tval2 = tval2; uptrap.tinst = tinst; @@ -141,10 +139,8 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, return 0; } -int sbi_misaligned_store_handler(u32 hartid, ulong mcause, - ulong addr, ulong tval2, ulong tinst, - struct sbi_trap_regs *regs, - struct sbi_scratch *scratch) +int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, + struct sbi_trap_regs *regs) { ulong insn; union reg_data val; @@ -221,7 +217,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, #endif } else { uptrap.epc = regs->mepc; - uptrap.cause = mcause; + uptrap.cause = CAUSE_MISALIGNED_STORE; uptrap.tval = addr; uptrap.tval2 = tval2; uptrap.tinst = tinst; diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c index 36702ca..b06b33f 100644 --- a/lib/sbi/sbi_trap.c +++ b/lib/sbi/sbi_trap.c @@ -247,15 +247,11 @@ void sbi_trap_handler(struct sbi_trap_regs *regs, msg = "illegal instruction handler failed"; break; case CAUSE_MISALIGNED_LOAD: - rc = sbi_misaligned_load_handler(hartid, mcause, mtval, - mtval2, mtinst, regs, - scratch); + rc = sbi_misaligned_load_handler(mtval, mtval2, mtinst, regs); msg = "misaligned load handler failed"; break; case CAUSE_MISALIGNED_STORE: - rc = sbi_misaligned_store_handler(hartid, mcause, mtval, - mtval2, mtinst, regs, - scratch); + rc = sbi_misaligned_store_handler(mtval, mtval2, mtinst, regs); msg = "misaligned store handler failed"; break; case CAUSE_SUPERVISOR_ECALL: |