diff options
| -rw-r--r-- | include/sbi/sbi_unpriv.h | 32 | ||||
| -rw-r--r-- | lib/sbi_ipi.c | 2 | ||||
| -rw-r--r-- | lib/sbi_misaligned_ldst.c | 4 |
3 files changed, 18 insertions, 20 deletions
diff --git a/include/sbi/sbi_unpriv.h b/include/sbi/sbi_unpriv.h index 930babd..2d9dbb9 100644 --- a/include/sbi/sbi_unpriv.h +++ b/include/sbi/sbi_unpriv.h @@ -15,29 +15,27 @@ #include <sbi/sbi_types.h> #define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ -static inline type load_##type(const type *addr, ulong mepc) \ +static inline type load_##type(const type *addr) \ { \ - register ulong __mepc asm ("a2") = mepc; \ - register ulong __mstatus asm ("a3"); \ + register ulong __mstatus asm ("a2"); \ type val; \ - asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ + asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ #insn " %1, %2\n" \ - "csrw "STR(CSR_MSTATUS)", %0" \ + "csrw "STR(CSR_MSTATUS)", %0" \ : "+&r" (__mstatus), "=&r" (val) \ - : "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc)); \ + : "m" (*addr), "r" (MSTATUS_MPRV)); \ return val; \ } #define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ -static inline void store_##type(type *addr, type val, ulong mepc) \ +static inline void store_##type(type *addr, type val) \ { \ - register ulong __mepc asm ("a2") = mepc; \ register ulong __mstatus asm ("a3"); \ - asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ + asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ #insn " %1, %2\n" \ - "csrw "STR(CSR_MSTATUS)", %0" \ + "csrw "STR(CSR_MSTATUS)", %0" \ : "+&r" (__mstatus) \ - : "r" (val), "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc)); \ + : "r" (val), "m" (*addr), "r" (MSTATUS_MPRV)); \ } DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu) @@ -57,16 +55,16 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld) DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw) DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw) -static inline u64 load_u64(const u64 *addr, ulong mepc) +static inline u64 load_u64(const u64 *addr) { - return load_u32((u32 *)addr, mepc) - + ((u64)load_u32((u32 *)addr + 1, mepc) << 32); + return load_u32((u32 *)addr) + + ((u64)load_u32((u32 *)addr + 1) << 32); } -static inline void store_u64(u64 *addr, u64 val, ulong mepc) +static inline void store_u64(u64 *addr, u64 val) { - store_u32((u32 *)addr, val, mepc); - store_u32((u32 *)addr + 1, val >> 32, mepc); + store_u32((u32 *)addr, val); + store_u32((u32 *)addr + 1, val >> 32); } #endif diff --git a/lib/sbi_ipi.c b/lib/sbi_ipi.c index 3b89d5d..609de0d 100644 --- a/lib/sbi_ipi.c +++ b/lib/sbi_ipi.c @@ -58,7 +58,7 @@ int sbi_ipi_send_many(struct sbi_scratch *scratch, u32 hartid = sbi_current_hartid(); if (pmask) - mask &= load_ulong(pmask, csr_read(CSR_MEPC)); + mask &= load_ulong(pmask); /* send IPIs to every other hart on the set */ for (i = 0, m = mask; m; i++, m >>= 1) diff --git a/lib/sbi_misaligned_ldst.c b/lib/sbi_misaligned_ldst.c index 8ab01c1..f1df3f0 100644 --- a/lib/sbi_misaligned_ldst.c +++ b/lib/sbi_misaligned_ldst.c @@ -93,7 +93,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause, val.data_u64 = 0; for (i = 0; i < len; i++) - val.data_bytes[i] = load_u8((void *)(addr + i), regs->mepc); + val.data_bytes[i] = load_u8((void *)(addr + i)); if (!fp) SET_RD(insn, regs, val.data_ulong << shift >> shift); @@ -169,7 +169,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause, return SBI_EILL; for (i = 0; i < len; i++) - store_u8((void *)(addr + i), val.data_bytes[i], regs->mepc); + store_u8((void *)(addr + i), val.data_bytes[i]); regs->mepc += INSN_LEN(insn); |