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2022-06-13lib: irqchip/plic: Add priority save/restore helpersSamuel Holland2-0/+24
These can be used by platform code to save the PLIC priority state, if it would otherwise be lost during non-retentive suspend. The platform is responsible for allocating all necessary storage. As a space optimization, store the saved priority values as 8-bit integers, since that is large enough to hold any priority value on the relevant platforms. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: irqchip/plic: Add context save/restore helpersSamuel Holland2-3/+54
These can be used by platform code to save the PLIC context state, if it would otherwise be lost during non-retentive suspend. The platform is responsible for allocating all necessary storage. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: irqchip/plic: Factor out a context init functionSamuel Holland4-53/+48
This simplifies both the callers and the callees by removing duplicated code and consolidating the error handling. It also fixes two bugs in the process: 1) ie_words was one too large when plic->num_src was a multiple of 32. 2) plic_set_ie takes a 32-bit mask, not a Boolean value, so the FPGA platforms previously only enabled one out of every 32 interrupts. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: irqchip/plic: Constify plic_data pointersSamuel Holland2-9/+11
None of the functions modify the passed-in plic_data, so mark it const. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: sbi_hsm: Assume a consistent resume addressSamuel Holland2-28/+22
The suspend code needs to know the resume address for two reasons: 1) Programming some hardware register or management firmware. Here we assume the hardware/firmware maintains its state between suspends, so it only needs to be programmed once at startup. 2) When a non-retentive suspend request ends up being retentive, due to lack of hardware support, pending interrupt, or for some other reason. However, the behavior here is not platform-dependent, and this can be handled in the generic hart suspend function. Since neither situation requires the platform-level suspend function to know the resume address, stop passing it to that function. Instead, handle the non-retentive to retentive situation generically. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: sbi_hsm: Call a device hook during hart resumeSamuel Holland2-0/+16
Non-retentive suspend states may require platform-specific actions during resume. For example, firmware may need to save and restore the values of custom CSRs. Add a hook to support this. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13platform: generic: add overrides for vendor extensionsMayuresh Chitale2-0/+32
Allow the vendor_ext_check and vendor_ext_provider APIs of the generic platform to be overridden by other platforms Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-06-13lib: sbi_trap: Redirect exception based on hedelegdramforever1-9/+6
HS-mode software can choose what exceptions to delegate to VS-mode using the hedeleg CSR. Synthetic VS/VU-mode exceptions should also honor hedeleg. They should be redirected to VS-mode if and only if delegated by HS-mode. Signed-off-by: dramforever <dramforever@live.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-06-01lib: sbi_illegal_insn: Add emulation for fence.tsoSamuel Holland2-1/+16
While OpenC906 appears to properly decode `fence.tso` as a fence instruction[1], the version of the C906 taped out in the Allwinner D1 does not, and raises illegal instruction. Handle this errata by emulating `fence.tso` as `fence rw, rw`. [1]: https://github.com/T-head-Semi/openc906/blob/30827e7f/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L2097 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-30lib: sbi_illegal_insn: Constify illegal_insn_tableSamuel Holland1-1/+1
This table does not need to be modified at runtime. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-30lib: sbi_timer: Drop unnecessary get_platform_ticks wrapperSamuel Holland1-6/+1
The device's timer_value callback is already the right prototype to use for the get_time_val function pointer. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-30lib: utils/fdt: Require match data to be constSamuel Holland4-5/+5
Match data stores hardware attributes which do not change at runtime, so it does not need to be mutable. Make it const. Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-30lib: sbi: fix system_opcode_insnXiang W1-0/+8
If the csr's operation comes from M mode, it should not be forwarded to low-privilege processing, this patch fixes this problem. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-14lib: utils/fdt: rename fdt_parse_max_hart_idJan Remes2-2/+2
The function returns the highest hart-id of the harts actually used in the system (enabled). Change the name to reflect this fact. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-14platform: generic: check if CPU node is enabledJan Remes1-0/+3
Ignore CPU nodes in FDT which are not enabled. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-14lib: utils: check if CPU node is enabledJan Remes3-1/+19
Ignore CPU nodes in FDT that are not enabled. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-14lib: utils/fdt: introduce fdt_node_is_enabled()Jan Remes2-0/+20
If an FDT node contains a "status" property and this property is not "ok" or "okay", this node should be ignored. Introduce a function that checks this. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-13lib: utils/irqchip: fix typo when checking for CPU nodeJan Remes1-1/+1
Fix typo in irqchip_imsic_update_hartid_table() when checking for CPU node. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-13platform: generic: Move Sifive platform overrides into own directoryAnup Patel4-6/+9
Let us move SiFive platform overrides for FU540 and FU740 into a separate directory so better maintainability. Other SoC vendors can also create their own directory under platform/generic. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13platform: generic: Generate platform override module list at compile-timeAnup Patel3-9/+13
Instead of having platform override module list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/gpio: Generate FDT gpio driver list at compile-timeAnup Patel4-10/+17
Instead of having FDT gpio driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/i2c: Generate FDT i2c adapter driver list at compile-timeAnup Patel3-9/+12
Instead of having FDT i2c adapter driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/ipi: Generate FDT ipi driver list at compile-timeAnup Patel3-7/+12
Instead of having FDT ipi driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/irqchip: Generate FDT irqchip driver list at compile-timeAnup Patel3-11/+16
Instead of having FDT irqchip driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/timer: Generate FDT timer driver list at compile-timeAnup Patel3-7/+12
Instead of having FDT timer driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/serial: Generate FDT serial driver list at compile-timeAnup Patel3-21/+26
Instead of having FDT serial driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/reset: Generate FDT reset driver list at compile-timeAnup Patel3-17/+20
Instead of having FDT reset driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13Makefile: Add support for generating C array at compile timeAnup Patel2-0/+88
Generating C array at compile time based on details provided by objects.mk is a very useful feature which will help us compile only a subset of drivers or modules. We add a bash script (carray.sh) which takes array details and object/variable list from command-line to generate a C source containing array of object/variable pointers. We also extend top-level makefile to use carray.sh whenever specified through objects.mk. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13Makefile: Allow generated C source to be anywhere in build directoryAnup Patel1-3/+3
The generated C source could be anywhere within build directory so let us update the make rule to comple generated C source accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi_platform: Add callback to populate HART extensionsAnup Patel2-4/+32
We add platform specific extensions_init() callback which allows platforms to populate HART extensions for each HART. For example, the generic platform can populate HART extensions from HART ISA string described in DeviceTree. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Add sbi_hart_update_extension() functionAnup Patel2-5/+41
We add sbi_hart_update_extension() function which allow platforms to enable/disable hart extensions. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Detect hart features only once for each hartAnup Patel1-3/+11
Currently, the hart_detect_features() is called everytime a hart is stopped and started again which is unnecessary work. We update hart_detect_features() to detect hart features only once for each hart. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Convert hart features into hart extensionsAnup Patel7-93/+86
Since past few years, we have been using "hart features" in OpenSBI to represent all optionalities and multi-letter extensions defined by the RISC-V specifications. The RISC-V profiles specification has taken a different approach and started assigning extension names for all optionalities which did not have any extension name previously. (Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) Inspired from the RISC-V profiles specification, we convert OpenSBI hart features into hart extensions. Going forward, we align the extension naming with RISC-V profiles specification. Currently, only "time CSR" and "AIA CSR" have not been assigned extension name but for everything else we have a name. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Fix AIA feature detectionAnup Patel1-4/+3
The AIA feature detection uses unnecessary goto which is not need and AIA case in sbi_hart_feature_id2string() does not break. This patch fixes both issues in AIA feature detection. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MENVCFG hart featureAnup Patel2-24/+14
If a hart implements privileged spec v1.12 (or higher) then we can safely assume that menvcfg CSR is present and we don't need MENVCFG as a hart feature. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MCOUNTINHIBT hart featureAnup Patel3-28/+19
If a hart implements privileged spec v1.11 (or higher) then we can safely assume that mcountinhibit CSR is present and we don't need MCOUNTINHIBT as a hart feature. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart featuresAnup Patel4-38/+16
If a hart implements privileged spec v1.10 (or higher) then we can safely assume that [m|s]counteren CSR are present and we don't need MCOUNTEREN and SCOUNTEREN as hart features. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Update the name of ISA string printed at boot timeAnup Patel1-1/+1
The ISA string printed at boot time is not the complete ISA string representing all single letter and multi-letter extensions rather it is base ISA string derived from misa CSR so let us update the boot print accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove 's' and 'u' from misa_string() outputAnup Patel1-1/+1
Both 's' and 'u' are not treated as ISA extensions since these are privilege modes so let's remove it from misa_string() output. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Detect and print privileged spec versionAnup Patel3-6/+63
It is possible to guess privileged spec versions based on the CSRs that where introduced in different privileged spec versions. In future, if we are not able guess privileged spec version then we can have platform provide it. We add privileged spec version as per-hart feature and try to guess it based on presence of mcounteren, mcountinhibit, and menvcfg CSRs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmfAtish Patra2-2/+10
MHPMEVENT3H-31H are defined in sscofpmf extension. Thus, they should be accessed only if sscofpmf is present. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-07include: sbi: Define SBI_PMU_HW_EVENT_MAX to 256Jun Liang Tan1-1/+1
Increase maximum number of PMU hardware events that can be mapped by OpenSBI to 256 Signed-off-by: Jun Liang Tan <junliang.tan@linux.starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim@linux.starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-28lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not availableAnup Patel1-1/+3
The mhpmevent3h to mhpmevent31h CSRs are available on RV32 only when Sscofpmf extension is available so mstatus_init() should set this CSRs only when Sscofpmf extension is available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-04-28lib: sbi: Implement Sstc extensionAtish Patra4-4/+57
Recently, Sstc extension was ratified. It defines stimecmp which allows the supervisor mode to directly update the timecmp value without the need of the SBI call. The hardware also can inject the S-mode timer interrupt direclty to the supervisor without going through the M-mode. To maintain backward compatibility with the older software, SBI call now uses stimecmp directly if the hardware supports. Implement the Sstc extension. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-28docs: pmu: Improve the PMU DT bindingsAtish Patra1-18/+31
The current DT binding description is misleading and confusing. Clarify the text and provide more examples. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-17lib: sbi/hart: preserve csr validation valueDmitry Dunaev1-3/+3
The OpenSBI hart init function hart_detect_features() try to read important CSRs but reasign the last read value to the variable that initially contains write probe value. So for series of CSRs (like PMPADDRx) the second CSR probe value will became the initial value of first probing CSR. To avoid of this issue the CSR read value should be saved in different variable. In this configuration the count of PMP will detect rightly if any PMPADDR is hardwired to zero. Signed-off-by: Dmitry Dunaev <dunaich@mail.ru> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-17include: correct the definition of MSTATUS_VSVincent Chen1-1/+1
Accordind to the RISC-V privileged specification, the VS filed is mstatus[10:9] instead of mstatus[24:23]. Modify the MSTATUS_VS to the correct value. Reported-by: I-Cheng Cheng <i-cheng.cheng@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-17lib: utils/serial: support 'reg-offset' propertyZong Li10-8/+23
reg-offset property is used for offset to apply to the mapbase from the start of the registers in 8250 UART. In Linux kernel, it has been handled in 8250 UART driver. dt-bindings: <linux>/Documentation/devicetree/bindings/serial/8250.yaml Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: irqchip/imsic: configure mstateenMayuresh Chitale1-0/+6
When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: sbi: Detect Smstateen CSRs at boot-timeMayuresh Chitale2-1/+28
Extend HART feature detection to discover Smstateen CSRs at boot-time and configure mstateen envcfg bit depending on availability of menvcfg CSR. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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