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2022-05-07lib: sbi: Remove MCOUNTINHIBT hart featureAnup Patel3-28/+19
If a hart implements privileged spec v1.11 (or higher) then we can safely assume that mcountinhibit CSR is present and we don't need MCOUNTINHIBT as a hart feature. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart featuresAnup Patel4-38/+16
If a hart implements privileged spec v1.10 (or higher) then we can safely assume that [m|s]counteren CSR are present and we don't need MCOUNTEREN and SCOUNTEREN as hart features. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Update the name of ISA string printed at boot timeAnup Patel1-1/+1
The ISA string printed at boot time is not the complete ISA string representing all single letter and multi-letter extensions rather it is base ISA string derived from misa CSR so let us update the boot print accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove 's' and 'u' from misa_string() outputAnup Patel1-1/+1
Both 's' and 'u' are not treated as ISA extensions since these are privilege modes so let's remove it from misa_string() output. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Detect and print privileged spec versionAnup Patel3-6/+63
It is possible to guess privileged spec versions based on the CSRs that where introduced in different privileged spec versions. In future, if we are not able guess privileged spec version then we can have platform provide it. We add privileged spec version as per-hart feature and try to guess it based on presence of mcounteren, mcountinhibit, and menvcfg CSRs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmfAtish Patra2-2/+10
MHPMEVENT3H-31H are defined in sscofpmf extension. Thus, they should be accessed only if sscofpmf is present. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-07include: sbi: Define SBI_PMU_HW_EVENT_MAX to 256Jun Liang Tan1-1/+1
Increase maximum number of PMU hardware events that can be mapped by OpenSBI to 256 Signed-off-by: Jun Liang Tan <junliang.tan@linux.starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim@linux.starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-28lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not availableAnup Patel1-1/+3
The mhpmevent3h to mhpmevent31h CSRs are available on RV32 only when Sscofpmf extension is available so mstatus_init() should set this CSRs only when Sscofpmf extension is available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-04-28lib: sbi: Implement Sstc extensionAtish Patra4-4/+57
Recently, Sstc extension was ratified. It defines stimecmp which allows the supervisor mode to directly update the timecmp value without the need of the SBI call. The hardware also can inject the S-mode timer interrupt direclty to the supervisor without going through the M-mode. To maintain backward compatibility with the older software, SBI call now uses stimecmp directly if the hardware supports. Implement the Sstc extension. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-28docs: pmu: Improve the PMU DT bindingsAtish Patra1-18/+31
The current DT binding description is misleading and confusing. Clarify the text and provide more examples. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-17lib: sbi/hart: preserve csr validation valueDmitry Dunaev1-3/+3
The OpenSBI hart init function hart_detect_features() try to read important CSRs but reasign the last read value to the variable that initially contains write probe value. So for series of CSRs (like PMPADDRx) the second CSR probe value will became the initial value of first probing CSR. To avoid of this issue the CSR read value should be saved in different variable. In this configuration the count of PMP will detect rightly if any PMPADDR is hardwired to zero. Signed-off-by: Dmitry Dunaev <dunaich@mail.ru> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-17include: correct the definition of MSTATUS_VSVincent Chen1-1/+1
Accordind to the RISC-V privileged specification, the VS filed is mstatus[10:9] instead of mstatus[24:23]. Modify the MSTATUS_VS to the correct value. Reported-by: I-Cheng Cheng <i-cheng.cheng@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-17lib: utils/serial: support 'reg-offset' propertyZong Li10-8/+23
reg-offset property is used for offset to apply to the mapbase from the start of the registers in 8250 UART. In Linux kernel, it has been handled in 8250 UART driver. dt-bindings: <linux>/Documentation/devicetree/bindings/serial/8250.yaml Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: irqchip/imsic: configure mstateenMayuresh Chitale1-0/+6
When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: sbi: Detect Smstateen CSRs at boot-timeMayuresh Chitale2-1/+28
Extend HART feature detection to discover Smstateen CSRs at boot-time and configure mstateen envcfg bit depending on availability of menvcfg CSR. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: sbi: Add Smstateen extension definesMayuresh Chitale1-0/+44
Smstateen extension provides a mechanism to plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-05lib: sbi: Enable Svpbmt extension in the menvcfg CSRAnup Patel1-0/+10
The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not available so we try to enable menvcfg.PBMTE bit irrespective whether Svpbmt is available or not. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-04-05lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSRAnup Patel1-1/+32
The bits to configure/enable Zicbo[m|z] extensions in the menvcfg CSR are WARL. We try to enable these bits irrespective whether these extensions are available or not because writes to these bits will be ignored if these extensions are not available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-04-05lib: sbi: Detect menvcfg CSR at boot timeAtish Patra2-1/+12
We add the menvcfg CSR as a HART feature and detect it at boot time using traping mechanism. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-04-05include: Add defines for [m|h|s]envcfg CSRsAnup Patel1-0/+27
The latest RISC-V privileged specification introduces xenvcfg CSRs to enable/disable certain features/extensions for lower privilege modes. This patch adds defines for these new [m|h|s]envcfg CSRs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-03-27include: Use static asserts for FW_DYNAMIC_INFO_xxx_OFFSET definesXiang W1-0/+35
Add static detection to prevent the modification of struct fw_dynamic_info from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-27include: Use static asserts for SBI_SCRATCH_xxx_OFFSET definesXiang W1-0/+60
Add static detection to prevent the modification of struct sbi_scratch from forgetting the modification of SBI_SCRATCH_xxx_OFFSET Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-27include: Use static asserts for SBI_PLATFORM_xxx_OFFSET definesXiang W1-0/+50
Add static detection to prevent the modification of struct sbi_platform from forgetting the modification of SBI_PLATFORM_xxx_OFFSET Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-27lib: Add error messages via conditional compilation for the futureXiang W1-1/+3
On 128-bit machines, sbi_load_xx/sbi_store_xx needs to be improved. Through this conditional compile, the corresponding implementation can be prompted to be added. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-27firmware: Fix code for accessing hart_count and stack_sizeXiang W1-1/+1
lwu exists under the current rv64 and should also exist under the rv128 in the future, so I modified the conditions of conditional compilation so that it can adapt to the future situation Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-27lib: pmp_set/pmp_get moved errors from runtime to compile timeXiang W1-2/+2
pmp_set/pmp_get calculates the location of the CSR register separately through conditional compilation. In the case of non-32-bit and 64-bit, we can report an error directly through #error without putting it at runtime Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-28lib: utils: serial: Initial commit of xlnx-uartliteAlistair Francis7-1/+144
Initial commit of the xlnx-uartlite device and FDT support. This was tested by running OpenSBI on a modified QEMU virt machine using the xlnx-uartlite for serial. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-28lib: sbi: Add a simple external interrupt handling frameworkAnup Patel7-34/+109
Currently, the external interrupt handling is scattered between sbi_init and sbi_trap. This patch moves all external interrupt handling into a simple framework called sbi_irqchip. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: sbi: verbose sbi_domain_root_add_memregionNikita Shubin2-3/+9
Be more verbose on region confict, print addresses in conflict. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-15lib: sbi: fix typo in is_region_subsetNikita Shubin1-1/+1
Fix typo in is_region_subset, regB_end should be calculated from regB. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-15lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups()Anup Patel2-3/+26
We should disable APLIC DT nodes in fdt_fixups() which are not accessible to the next booting stage based on currently assigned domain. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add FDT based driver for APLICAnup Patel5-0/+222
We add simple FDT irqchip driver for APLIC so that generic platform (and other FDT based platforms) can utilize common APLIC initialization library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add APLIC initialization libraryAnup Patel3-0/+327
We add simple APLIC initialization library which is independent of hardware description format (FDT or ACPI). This APLIC initialization library can be used by custom OpenSBI platform support to setup APLIC domains. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups()Anup Patel2-4/+45
We should disable IMSIC DT nodes in fdt_fixups() which are not accessible to the next booting stage based on currently assigned domain. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add FDT based driver for IMSICAnup Patel6-0/+230
We add simple FDT irqchip driver for IMSIC so that generic platform (and other FDT based platforms) can utilize common IMIC library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add IMSIC libraryAnup Patel3-0/+338
We add simple IMSIC library which is independent of hardware description format (FDT or ACPI). This IMSIC library can be used by custom OpenSBI platform support to setup IMSIC for external interrupts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: sbi: Enable mie.MEIE bit for IPIs based on external interrupts.Anup Patel2-5/+8
We can have IPIs based on external interrupts provided by devices such as AIA IMSIC so we should enable mie.MEIE bit at appropriate places in generic library. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15include: sbi: Introduce nascent_init() platform callbackAnup Patel2-0/+28
We introduce nascent_init() platform callback which will allow platforms to do very early initialization of platform specific per-HART CSRs and per-HART devices. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Allow multiple FDT irqchip driversAnup Patel1-7/+30
We can have multiple FDT irqchip drivers to be probed when a RISC-V system has different types of interrupt controller in a hierarchy. This will be certainly the case when a RISC-V system has both RISC-V AIA IMSIC and RISC-V AIA APLIC implemented. We extend simple FDT irqchip framework to allow multiple FDT irqchip drivers to be used for same RISC-V platform. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: sbi: Add sbi_trap_set_external_irqfn() APIAnup Patel2-0/+31
This patch adds sbi_trap_set_external_irqfn() API which can be used by OpenSBI platform code to set a callback function for external interrupts. The RISC-V AIA IMSIC driver will use this API to implement inter-processor interrupts on-top-of MSIs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: sbi: Use AIA CSRs for local interrupts when availableAnup Patel1-11/+46
We should use AIA CSRs to process local interrupts whenever AIA is available. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: sbi: Detect AIA CSRs at boot-timeAnup Patel2-1/+14
We extend HART feature detection to discover AIA CSRs at boot-time. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15include: sbi: Add AIA related CSR definesAnup Patel1-0/+76
The RISC-V AIA specification improves handling of per-HART local interrupts in a backward compatible manner. This patch adds defines for the new RISC-V AIA CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-04lib: utils/serial: Round UART8250 baud rate divisor to nearest integerVF_SDK_510_V1.2.1VF_SDK_510_V1.1.2VF_SDK_510_V1.0.2SDK_v2.3.3SDK_v2.3.0SDK_v2.1.1SDK_v2.1.0Jakub Luzny1-1/+1
Previously, it was rounded down and that gives suboptimal results when non-standard clock sources or baud rates are used. Signed-off-by: Jakub Luzny <jakub.luzny@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04lib: fix compilation when strings.h is includedPetro Karashchenko5-89/+19
In a systems that provide strings.h and it is included together with sbi_bitops.h the compilation error appears. The ffs() and fls() are provided by strings.h Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04Makefile: fix build with binutils 2.38Aurelien Jarno1-1/+8
From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: CC lib/sbi/sbi_tlb.o <<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages: <<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i' make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1 The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04lib: sbi: Disable interrupt and inhibit counting in M-mode during initAtish Patra1-0/+18
Currently, the mhpmevent CSRs are untouched during hart init during cold/warm boot. Ideally, we should clear out all the bits except overflow and MINH bit. That is required to disable overflow interrupt and inhibit counting in M-mode to avoid any spurious interrupts before perf start. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04lib: sbi: Disable interrupt during config matchingAtish Patra2-4/+9
PMU overflow interrupt should be disabled durinig initial configuration of counters. They should be enabled while starting counters. Fixes: 730f01bb41a6 ("lib: sbi: Support sscofpmf extension in OpenSBI") Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04lib: sbi: Map only the counters enabled in hardwareAtish Patra1-1/+5
The counter mapping in DT may be incorrect if all the counters specified in the mapping are actually not physically present in the hardware. OpenSBI should only keep a mapping of counters enabled in hardware and defined in DT. This assume that all the programmable hpmcounters are consecutive as it doesn't make sense to build a system with sparse hpmcounters. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-01-21lib: fix pointer of type 'void *' used in arithmeticJukka Laitinen13-27/+27
Using "void *" in arithmetic causes errors with strict compiler settings: "error: pointer of type 'void *' used in arithmetic [-Werror=pointer-arith]" Avoid these by calculating on "char *" where 1-byte data size is assumed. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae> Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-06-24 15:09:22 +0300