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path: root/include/sbi/riscv_asm.h
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2020-05-07lib: sbi: Improve misa_string() implementationAnup Patel1-13/+2
The RISC-V ISA string does not follow alphabetical order. Instead, we have a RISC-V specific ordering of extensions in the RISC-V ISA string. This patch improves misa_string() implementation to return a valid RISC-V ISA string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18lib: sbi: Update pmp_get() to return decoded size directlyBin Meng1-1/+1
Currently pmp_get() returns the log2 length of the PMP memory region size. The caller has to calculate the size based on that and the same codes are duplicated. Update this function to return decoded size directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-13include: Make sbi_current_hartid() as macro in riscv_asm.hAnup Patel1-0/+2
The sbi_current_hartid() being a regular function is quite expensive because for callers it is a function call instead of a direct CSR read. This patch converts sbi_current_hartid() into a macro in riscv_asm.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-10lib: sbi: Fix coding style issuesBin Meng1-3/+3
This fixes various coding style issues found in the SBI codes. No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-08include: Move bits related defines and macros to sbi_bitops.hAnup Patel1-2/+0
The right location for all bits related defines and macros is sbi_bitops.h hence this patch. With this patch, the sbi_bits.h is redundant so we remove it. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-11-27lib: Add error detection for misa_extensionXiang W1-3/+11
Add assertions for misa_extension to prevent incoming illegal characters. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-11-26lib: Fix CPU capabilities detection functionXiang Wang1-10/+6
On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-05-24lib: Factor-out TLB management from IPI managementAnup Patel1-3/+0
This patch factor-out TLB management from IPI management to separate sources sbi_tlb.c and sbi_tlb.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-05-21lib: Flush everything when remote TLB flush range is too largeAnup Patel1-1/+3
On latest Linux kernel (i.e. 5.2-rc1), we get large TLB flush request for user space addresses (typically, start=x and end=-1). This is caused by Linux kernel commit a21344dfc6 ("riscv: fix sbi_remote_sfence_vma{,_asid}"). It's not practical to execute large number of sfence instructions for a large TLB flush range because it takes too much time and eventually causes CPU stall in Linux kernel. This patch addresses above issue by upgrading TLB flush range to TLB flush all whenever TLB flush range is greater than 1GB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-04-24all: run clang-format and update checked-in filesOlof Johansson1-67/+74
Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-24all: Annotate some tables to have clang-format leave them aloneOlof Johansson1-0/+4
One of the shortcomings of clang-format is that it doesn't allow for aligned define tables, which is used for a number of constants. Add annotation to disable the automatic formatting where needed. Signed-off-by: Olof Johansson <olof@lixom.net>
2019-03-12lib: Implement sfence.vma correctly.Atish Patra1-0/+5
Currently, OpenSBI doesn't distinguish between sfence.vma and sfence.vm asid calls. Moreover, it ignores the page ranges and just flush entire TLB everytime. Fix the sfence implementation by keeping all the tlb flush info in scratch area. The relevant Linux kernel code was added by https://patchwork.kernel.org/project/linux-riscv/list/?series=89695 However, this patch is backward compatible with older version kernel that doesn't have the above patches as well. Fixes #87 Signed-off-by: Atish Patra <atish.patra@wdc.com>
2019-02-05riscv_asm.h: Use CSR_<FOO> instead of <foo> for csr_read()Olof Johansson1-3/+5
Some toolchains might not have all the CSRs available (as seen with GCC 7.2). So, instead use the defined CSR_ values. Signed-off-by: Olof Johansson <olof@lixom.net>
2019-01-24all: Update copyright header in all filesAnup patel1-3/+3
This patch updates copyright header in all files as follows: 1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line 2. Change copyright year to 2019 for Western Digital Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-22lib: Add atomic bit set/clear operations.Atish Patra1-0/+2
Add addtional functionlities for set/clear bits atomically. Signed-off-by: Atish Patra <atish.patra@wdc.com>
2019-01-02include: Move RISCV_TRAP_REGS_xyz defines to sbi_trap.hAnup Patel1-40/+0
The struct sbi_trap_regs related defines RISCV_TRAP_REGS_xyz should be in sbi_trap.h so that we can keep these defines in-sync with changes in struct sbi_trap_regs. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-02include: Move RISCV_PLATFORM_xyz defines to sbi_platform.hAnup Patel1-5/+0
The struct sbi_platform related defines RISCV_PLATFORM_xyz should be in sbi_platform.h so that we can keep these defines in-sync with changes in struct sbi_platform. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-02include: Move RISCV_SCRATCH_xyz defines to sbi_scratch.hAnup Patel1-12/+0
The struct sbi_scratch related defines RISCV_SCRATCH_xyz should be in sbi_scratch.h so that we can keep these defines in-sync with changes in struct sbi_scratch. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-02include: Replace #csr with __ASM_STR(csr) in csr_xyz() macrosAnup Patel1-5/+5
We replace #csr with __ASM_STR(csr) in all csr_xyz() macros so that we can pass CSR number instead of CSR name when GCC is not aware of CSR name. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-02include: Remove redundant csr_read_n() and csr_write_n()Anup Patel1-19/+2
The patch removes redundant csr_read_n() and csr_write_n() because same thing can be achieved by using __ASM_STR() macro in csr_read() and csr_write() macros. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-22firmware: Don't depend on PLAT_HART_COUNT and PLAT_HART_STACK_SIZEAnup Patel1-0/+5
The hart_count and hart_stack_size information is already available in "struct sbi_platform" so we use that instead of depending on PLAT_HART_COUNT and PLAT_HART_STACK_SIZE. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11Initial commit.Anup Patel1-0/+244
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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