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Currently, the root domain memory regions are fixed in generic
code but some of the platforms may want to explicitly define
memory regions for the root domain.
This patch adds optional domains_root_regions() platform callback
which platforms can use to provide platform specific root domain
memory regions. Due to this changes, the root domain should also
undergo all sanity checks (just like regular domain) so we use
sbi_domain_register() to register root domain.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Currently, we have fixed TLB flush types supported by the
remote TLB library. This approach is not flexible and does
not allow custom local TLB flush function. For example,
after updating PMP entries on a set of HARTs at runtime,
we have to flush TLB on these HARTs as well.
To support custom local TLB flush function, we replace the
"type" field of "struct sbi_tlb_info" with a local TLB flush
function pointer. We also provide definitions of standard TLB
flush operations (such as fence_i, sfence.vma, hfence.vvma,
hfence.gvma, etc).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We introduce sbi_trap_exit() API which can help non-firmware
(i.e. generic or platform) code to force exit trap/interrupt
handling and resume execution at context pointed by parameter
"const struct sbi_trap_regs *regs".
This new sbi_trap_exit() API will help Keystone Enclave project
to resume execution of enclave from custom SBI call handler.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We had added args pointer in ecall handler to ensure that ecall
handler only implements functionality and does not deal with
SBI calling convention. This also helped us to keep SBI calling
convention related code in one place at sbi_ecall_handler().
The Keystone Enclavce project needs access to the trap regsiters
in their ecall handler so that they can context switch enclaves
in custom SBI calls. To help the Keystone Enclave project, we
replace the args pointer in ecall handler parameter with a const
pointer to trap registers.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The domain_get() platform callback function is now redundant
because fdt_domain_populate() register new domain explicitly
using the sbi_domain_register() function.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We add sbi_domain_register() function to help platform code register
a new domain explicitly instead of depending on domain_get() platform
callback. This function will eventually help us completely remove the
domain_get() platform callback.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We introduce domains_init() platform operation which can be used by
platform support to initialize/populate domains in the coldboot path.
The domains_init() is called late in the coldboot sequence from the
sbi_domain_finalize() so sbi_printf() can be used by platform support
to print errors/warnings at time of populating domains.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We should use lower bits for domain memory region access permissions
and higher bits for other domain memory region attributes. This helps
us use same bit assignment for parsing domain memory region access
permissions from device tree.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The SBI SRST extension has been accepted and merged in the latest
SBI v0.3-draft specification.
(Refer, https://github.com/riscv/riscv-sbi-doc)
It allows to S-mode software to request system shutdown, cold reboot,
and warm reboot.
This patch implements SBI SRST extension as a replacement of the
legacy sbi_shutdown() call of SBI v0.1 specification.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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To implement the SBI SRST extension, we need two platform operations
for system reset:
1) system_reset_check() - This operation will check whether given
reset type and reason are supported by the platform
2) system_reset() - This operation will do the actual platform
system reset and it will not return if reset type and reason
are supported by the platform
This patch updates system reset related code everywhere as-per above.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We can now use the standard SBI SRST extension reset types instead
of the opensbi specific (SBI_PLATFORM_RESET_xyz) reset types hence
remove related opensbi specific defines. The "platform_" prefix of
the reset type parameter of sbi_system_reset() function should also
be removed.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We extend the SBI ecall interface header for the SBI SRST extension
recently accepted in SBI specification v0.3-draft.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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As per RISC-V privilege specification, a platform may choose to implement
a coarser granularity scheme for PMP addresses. In that case, we shouldn't
allow any pmp region size smaller than the platform supports. A platform
may not also implement all the bits for a PMP address specified in the priv
specification.
The pmp range granularity and address bits should be detected dynamically
before detecing PMP regions. Any pmp modification request beyond these detected
value must not succeed.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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We extend boot prints to display details of each domain. In the
process, we remove sbi_hart_pmp_dump() because it shows redundant
information which domain details already show.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The sbi_hart_pmp_get() and sbi_hart_pmp_check_addr() functions
are not used anymore hence this patch removes these functions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The sbi_hsm_hart_start() should consider the domain under which we
are trying to start the HART. This will help ensure that HART A can
start HART B only if both HARTs A and B belong to the same domain.
We also have a special case when we bring-up boot HART of non-root
domains in sbi_domain_finalize() where we should skip domain checks
in sbi_hsm_hart_start(). To achieve this, sbi_hsm_hart_start() should
do domain checks only when domain parameter is non-NULL.
This patch extends sbi_hsm_hart_start() as-per above.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The sbi_hsm_hart_started_mask() API should take one more parameter
to allow caller specify domain under which started_mask is being
generated. Further, the sbi_hsm_hart_started_mask() depends on
sbi_hsm_hart_get_state() which also should return HART state under
specified domain.
This patch updates both sbi_hsm_hart_started_mask() and
sbi_hsm_hart_get_state() as-per above.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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An OpenSBI domain is a logical entity representing a set of HARTs
and a set of memory regions for these HARTs.
The OpenSBI domains support will allow OpenSBI platforms and previous
booting stage (i.e. U-Boot SPL, Coreboot, etc) to partition a system
into multiple domains where each domain will run it's own software.
For inter-domain isolation, OpenSBI will eventually use various HW
features such as PMP, ePMP, IOPMP, SiFive shield, etc but initial
implementation only use HW PMP support.
This patch provides initial implementation of OpenSBI domains where
we have a root/default domain and OpenSBI platforms can provide
non-root/custom domains using domain_get() callback.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The sbi_hartmask_test_hart() does not modify hartmask so the
hartmask pointer parameter should be declared const.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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The hartid parameter of sbi_hart_init() is not used anywhere in
sbi_hart_init() implementation so let's remove it.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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We factor-out PMP configuration from sbi_hart_init() as a separate
sbi_hart_pmp_configure() function and do the PMP configuration very
late in coldboot and warmboot path just before platform_final_init().
Eventually, this enable us to configure PMP totally based on OpenSBI
domain where OpenSBI domains can be parsed from device-tree in any of
the platform operations except platform_final_init().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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The pmp_region_xyz() callbacks are not required in sbi_platform_operations
because we will be using OpenSBI domain memory regions to program the
PMP CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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The sbi_ecall.h and sbi_trap.h are not required to be included in
sbi_platform.h hence we remove it. This way sources requiring
these headers will have to explicitly include it thereby reducing
implicit includes.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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%s/scatch/scratch
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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We extend sbi_hart_pmp_check_addr() API so that users can specify
privilege mode of the address for checking PMP access permissions.
To achieve this, we end-up converting "unsigned long *size" parameter
to "unsigned long *log2len" for pmp_get() implementation so that we
can deal with regions of "1UL << __riscv_xlen" size in a special case
in sbi_hart_pmp_check_addr() implementation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The sbi_scratch already has provision to specify the next stage mode
so we can leverage this to specify start mode to sbi_hsm_hart_start().
In future, this will be useful in providing SBI calls to U-mode on
embedded cores where we M-mode and U-mode but no S-mode.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and
CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that
it matches latest RISC-V privilege spec.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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This patch does following cosmentic changes to riscv_encoding.h:
1. Re-organize CSR defines to match CSR listing in latest RISC-V
privilege spec
2. Rename CSR_HCOUNTERNEN to CSR_HCOUNTEREN
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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A RISC-V platform can leave unimplemented MHPM counters hard-wired
to zero. We extend hart_detect_features() to detect MHPM counters
which are accessible and not hard-wired to zero. We also print
number of available MHPM counters as part of boot prints.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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As-per latest RISC-V privilege spec up to 64 PMP entries are supported.
Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR
fields are WARL and may be hardwired to zero.
This patch improves PMP CSR detection and progamming considering
above facts.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The SBI_HART_HAS_PMP feature is redundant because we already
have number of PMP regions returned by sbi_hart_pmp_count().
Checking whether PMP is supported for a HART can be simply done
by checking non-zero value returned by sbi_hart_pmp_count().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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This commit add an implementation of sbi_strncmp.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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The value assigned to x by the shift assignment in the last if block of
ffs/fls is never read. Remove it.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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This patch updates OpenSBI version to 0.8 as part of
release preparation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We should only return valid error codes from SBI ecalls as
defined by the RISC-V SBI spec.
To achieve this:
1. We use SBI_Exxxx defines for OpenSBI internal errors with
error values starting from -1000
2. We use SBI_ERR_xxxx defines for errors defined by SBI spec
3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines
which are semantically same
4. We throw a error print and force return error code to
SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid
error code being returned to S-mode
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
__sbi_hfence_vvma_asid_va() functions are swapped so we fix it.
Currently, we did not face any issues because QEMU does a full
TLB flush for all HFENCE instructions.
We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
instruction encoding.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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It is not mandatory for a RISC-V systems to implement all PMP
regions so we have to check all PMPADDRx CSRs to determine excat
number of supported PMP regions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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It makes more sense to have scratch pointer as parameter in
HART feature APIs because:
1. We already have scratch pointer at places where these APIs
are used.
2. This is consistent with lot of other APIs in sbi_hart.h
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We do following improvements for get_feature_str():
1. We should return "none" from get_feature_str() no features
available instead of sbi_boot_prints() explicitly handling
failure.
2. We don't need to return failure (just like misa_xlen())
because we are returning "none" for no features and we are
truncating output when space is not available.
3. Based on 1 and 2, the sbi_boot_prints() can be further
simplified.
4. No need for two char[] in sbi_boot_prints()
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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We have now clear distinction between platform and hart features.
Modify the boot print messages to print hart specific features in
a string format.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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We have now clear distinction between platform and hart features.
Modify the boot print messages to print platform features in a string
format. In the process, this patch moved relatively larger functions
to its own file from platform.h header file.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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As per the RISC-V specification, time value can be obtained from a time
CSR implemented in hardware or a MMIO based IP block. Qemu virt machine
already supports timer csr while CLINT provides the timer for other
platforms.
Implement a hart specific timer feature that can be detected at runtime.
As CSR based timer implementation are faster than MMIO address based, it
is always preferred over MMIO based one.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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PMP & performance counters belong to a hart rather than a platform.
In addition to that, these features enable reading/writing from a
particular csr. Thus, they can be detected and set at runtime rather
than compile time.
Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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There may be some features which are hart specific rather than a platform
specific feature. Add a framework to support that.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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There may be few common mathematics helper functions which can be used
anywhere in OpenSBI project.
Add a separate math helper function file to add these functions.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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As RISC-V ISA allows many CSRs such as pmp, s/mcounteren to be optional
in hardware, OpenSBI should provide an option to dynamically detect
these csr access capability at run time.
Implement a csr read/write access check helper macros.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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Unprivileged trap handler can be reused for any cases where the executing
code expects a trap.
Rename it to "expected" trap handler as it will be used in other cases in
future.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
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The RISC-V ISA string does not follow alphabetical order. Instead,
we have a RISC-V specific ordering of extensions in the RISC-V ISA
string. This patch improves misa_string() implementation to return
a valid RISC-V ISA string.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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