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path: root/lib/sbi/sbi_hart.c
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2021-03-03lib: sbi: Add sbi_hart_reinit() functionAnup Patel1-12/+17
We add sbi_hart_reinit() function which will re-initialize HART CSRs assuming HART features are already detected. This new function will be useful in re-initializing HART after it resumes from HSM SUSPENDED state. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-12-04lib: sbi: Fix sbi_hart_switch_mode() for u-modeAnup Patel1-3/+5
We should check and access N-extension CSRs in sbi_hart_switch_mode() when next_mode is u-mode because N-extension is optional. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-26lib: sbi: Detect PMP granularity and number of address bitsAtish Patra1-4/+58
As per RISC-V privilege specification, a platform may choose to implement a coarser granularity scheme for PMP addresses. In that case, we shouldn't allow any pmp region size smaller than the platform supports. A platform may not also implement all the bits for a PMP address specified in the priv specification. The pmp range granularity and address bits should be detected dynamically before detecing PMP regions. Any pmp modification request beyond these detected value must not succeed. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-10-21lib: sbi: Display domain details in boot printsAnup Patel1-34/+10
We extend boot prints to display details of each domain. In the process, we remove sbi_hart_pmp_dump() because it shows redundant information which domain details already show. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20lib: sbi: Configure PMP based on domain memory regionsAnup Patel1-15/+22
The PMP configuration on each HART should be only based on the memory regions of the assigned domain because each domain includes a memory region to protect the underlying firmware. This patch updates the sbi_hart_pmp_configure() function accordingly. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20lib: sbi: Remove redundant sbi_hart_pmp_xyz() functionsAnup Patel1-42/+0
The sbi_hart_pmp_get() and sbi_hart_pmp_check_addr() functions are not used anymore hence this patch removes these functions. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20lib: sbi: Remove redundant hartid parameter from sbi_hart_init()Anup Patel1-7/+7
The hartid parameter of sbi_hart_init() is not used anywhere in sbi_hart_init() implementation so let's remove it. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-20lib: sbi: Configure PMP late in coldboot and warmboot pathAnup Patel1-2/+2
We factor-out PMP configuration from sbi_hart_init() as a separate sbi_hart_pmp_configure() function and do the PMP configuration very late in coldboot and warmboot path just before platform_final_init(). Eventually, this enable us to configure PMP totally based on OpenSBI domain where OpenSBI domains can be parsed from device-tree in any of the platform operations except platform_final_init(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-20include: sbi: Remove pmp_region callbacks from sbi_platform_operationsAnup Patel1-13/+1
The pmp_region_xyz() callbacks are not required in sbi_platform_operations because we will be using OpenSBI domain memory regions to program the PMP CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-20include: sbi: Remove redundant includes from sbi_platform.hAnup Patel1-0/+1
The sbi_ecall.h and sbi_trap.h are not required to be included in sbi_platform.h hence we remove it. This way sources requiring these headers will have to explicitly include it thereby reducing implicit includes. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-25lib: sbi: Fix PMP CSR detectionPragnesh Patel1-1/+1
HiFive unleashed currently implements fewer than 56 bits of physical address so existing PMP CSR detection is broken. PMP address register encodes bits 55-2 of a 56-bit physical address, Not all physical address bits may be implemented, So just check minimum 1 bit. Fixes: 74d1db706293 ("lib: sbi: Improve PMP CSR detection and progamming") Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-09-16lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() APIAnup Patel1-7/+21
We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-09include: Rename ECALL defines to match latest RISC-V specAnup Patel1-1/+1
We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Detect and print MHPM counters at boot-timeAnup Patel1-0/+17
A RISC-V platform can leave unimplemented MHPM counters hard-wired to zero. We extend hart_detect_features() to detect MHPM counters which are accessible and not hard-wired to zero. We also print number of available MHPM counters as part of boot prints. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Improve PMP CSR detection and progammingAnup Patel1-24/+48
As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Remove redundant SBI_HART_HAS_PMP featureAnup Patel1-14/+1
The SBI_HART_HAS_PMP feature is redundant because we already have number of PMP regions returned by sbi_hart_pmp_count(). Checking whether PMP is supported for a HART can be simply done by checking non-zero value returned by sbi_hart_pmp_count(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-06-20lib: Don't return any invalid error from SBI ecallAnup Patel1-1/+1
We should only return valid error codes from SBI ecalls as defined by the RISC-V SBI spec. To achieve this: 1. We use SBI_Exxxx defines for OpenSBI internal errors with error values starting from -1000 2. We use SBI_ERR_xxxx defines for errors defined by SBI spec 3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines which are semantically same 4. We throw a error print and force return error code to SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid error code being returned to S-mode Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-06-18lib: Fix the SBI_HART_HAS_MCOUNTEREN feature checkAlistair Francis1-1/+1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-18lib: Don't print delegation CSRs if there is no S-ModeAlistair Francis1-0/+4
If the platform doesn't support S-Mode don't print the delegation registers. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-08lib: Add RISC-V hypervisor v0.6.1 supportAnup Patel1-0/+1
To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19lib: sbi_hart: Detect number of supported PMP regionsAnup Patel1-36/+80
It is not mandatory for a RISC-V systems to implement all PMP regions so we have to check all PMPADDRx CSRs to determine excat number of supported PMP regions. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-05-19lib: sbi: Few cosmetic improvements to HART feature detectionAnup Patel1-20/+12
This patch does few cosmetic improvements to HART feature detection: 1. Remove sbi_ perfix from HART feature detection functions because all local/static functions in sbi_hart.c don't have sbi_ prefix 2. Remove sbi_hart_set_feature() because it's quite small and local/static in sbi_hart.c Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19include: sbi: Use scratch pointer as parmeter in HART feature APIsAnup Patel1-23/+23
It makes more sense to have scratch pointer as parameter in HART feature APIs because: 1. We already have scratch pointer at places where these APIs are used. 2. This is consistent with lot of other APIs in sbi_hart.h Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19lib: sbi: Improve get_feature_str() implementation and usageAnup Patel1-7/+11
We do following improvements for get_feature_str(): 1. We should return "none" from get_feature_str() no features available instead of sbi_boot_prints() explicitly handling failure. 2. We don't need to return failure (just like misa_xlen()) because we are returning "none" for no features and we are truncating output when space is not available. 3. Based on 1 and 2, the sbi_boot_prints() can be further simplified. 4. No need for two char[] in sbi_boot_prints() Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19lib: sbi: detect features before everything else in sbi_hart_init()Anup Patel1-3/+3
We should detect HART features in sbi_hart_init() before mstatus_init(), delegate_traps() and pmp_init(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-10lib: Add hart features in boot time printAtish Patra1-0/+77
We have now clear distinction between platform and hart features. Modify the boot print messages to print hart specific features in a string format. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10lib: timer: Provide a hart based timer featureAtish Patra1-0/+6
As per the RISC-V specification, time value can be obtained from a time CSR implemented in hardware or a MMIO based IP block. Qemu virt machine already supports timer csr while CLINT provides the timer for other platforms. Implement a hart specific timer feature that can be detected at runtime. As CSR based timer implementation are faster than MMIO address based, it is always preferred over MMIO based one. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10platform: Move platform features to hartAtish Patra1-8/+60
PMP & performance counters belong to a hart rather than a platform. In addition to that, these features enable reading/writing from a particular csr. Thus, they can be detected and set at runtime rather than compile time. Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10lib: Add support for hart specific featuresAtish Patra1-0/+23
There may be some features which are hart specific rather than a platform specific feature. Add a framework to support that. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10lib: Create a separate math helper function fileAtish Patra1-13/+1
There may be few common mathematics helper functions which can be used anywhere in OpenSBI project. Add a separate math helper function file to add these functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10lib: Rename unprivileged trap handlerAtish Patra1-4/+4
Unprivileged trap handler can be reused for any cases where the executing code expects a trap. Rename it to "expected" trap handler as it will be used in other cases in future. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-04-27lib: No need to provide default PMP region using platform callbacksAnup Patel1-9/+15
The default (usually last) PMP region provides S-mode access to complete memory range not covered by other PMP regions. Currently, the default PMP region is described as platform specific PMP region which is not appropriate because all platforms need it and default PMP region should be part of generic library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-17lib: Support vector extensionAtish Patra1-1/+8
Enable vector context in mstatus by updating the corresponding bits in mstatus if vector extension is supported by the hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-28lib: Optimize unpriv load/store implementationAnup Patel1-29/+7
This patch optimize unpriv load/store implementation by having dedicated unpriv trap handler (just like KVM RISC-V). As a result of this optimization: 1. We have reduced roughly 13+ instruction in all unpriv load/store functions. The reduced instruction also include two function calls. 2. Per-HART trap info pointer in scratch space is now redundant hence removed. 3. The sbi_trap_handler() is now much cleaner because we don't have to handle unpriv load/store traps. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-18lib: sbi: Update pmp_get() to return decoded size directlyBin Meng1-12/+4
Currently pmp_get() returns the log2 length of the PMP memory region size. The caller has to calculate the size based on that and the same codes are duplicated. Update this function to return decoded size directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-13include: Make sbi_current_hartid() as macro in riscv_asm.hAnup Patel1-8/+0
The sbi_current_hartid() being a regular function is quite expensive because for callers it is a function call instead of a direct CSR read. This patch converts sbi_current_hartid() into a macro in riscv_asm.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-13include: Make sbi_hart_id_to_scratch() as macroAnup Patel1-8/+0
The sbi_hart_id_to_scratch() just forwards call to firmware specific hartid_to_scratch() callback so we make sbi_hart_id_to_scratch() as macro in sbi_scratch.h instead of regular function in sbi_hart.c. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-11lib: sbi_hart: Remove HART available mask and related APIsAnup Patel1-29/+0
The HART available mask and related APIs are now totally redundant because of more extensive HART state machine implemented by sbi_hsm. Due to above, we remove HART available mask and related APIs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-11lib: Move all coldboot wait APIs to sbi_init.cAnup Patel1-70/+0
The coldboot wait APIs are only used by sbi_init.c so no point in having coldboot related code in sbi_hart.c. As per-above rationale, we move all coldboot wait related APIs to sbi_init.c as static/local functions. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-10lib: sbi: Fix coding style issuesBin Meng1-2/+2
This fixes various coding style issues found in the SBI codes. No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-08include: Move bits related defines and macros to sbi_bitops.hAnup Patel1-1/+1
The right location for all bits related defines and macros is sbi_bitops.h hence this patch. With this patch, the sbi_bits.h is redundant so we remove it. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-07lib: Check MSIP bit after returning from WFIAtish Patra1-2/+5
As per the RISC-V privilege specification, WFI can be implemented as a NOP. Software should ensure that relevant interrupt pending bits are set. Otherwise, loop back to WFI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-24lib: Implement hart hotplugAtish Patra1-0/+25
This patch adds support for hart hotplug in OpenSBI using a generic WFI based approach. Hart hotplug can be achieved via SBI HSM extension which allows supervisor mode software to start or stop any harts anytime. Any platform wishes to implement platform specific hart hotplug must implement both hart_start and hart_stop in addition to enable platform feature SBI_PLATFORM_HAS_HART_HOTPLUG. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-19lib: Print interrupt and exception delegation in boot printsAnup Patel1-2/+13
We print MIDELEG and MEDELEG CSRs as part of boot prints so that boot log shows the interrupts and exceptions delegated to S-mode. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-19lib: Don't check MIDELEG and MEDELEG at end of delegate_traps()Anup Patel1-5/+0
The MIDELEG and MEDELEG CSR checks at end of delegate_traps() were added for initial bring-up on SiFive Unleashed and QEMU. These checks are not required any more and in-future these checks can cause failures because some of the MIDELEG/MEDELEG bits will be hard-wired to 0 or 1. For related discussion, refer github issue: https://github.com/riscv/opensbi/issues/157 Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-07lib: save/restore MIE CSR in sbi_hart_wait_for_coldboot()Anup Patel1-0/+7
Currently, sbi_hart_wait_for_coldboot() leaves MIE.MSIP bit set when it returns which is not correct because MIE.MSIP should be left enabled only by sbi_ipi_init(). This patch does save/restore of MIE CSR to ensure that MIE CSR is in original state after sbi_hart_wait_for_coldboot() returns. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-12-16lib: Extend trap redirection for hypervisor v0.5 specAnup Patel1-2/+0
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-12-16lib: Delegate guest page faults to HS-modeAnup Patel1-6/+12
As-per RISC-V hypervisor v0.5 spec, we have new guest page faults which need to be delegated to HS-mode. Also, we can have bits in in MIDELEG and MEDELEG hardwired to 1 which means we need to fix the sainty check on these CSRs at the end of delegate_traps() function. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-10-02lib: Fix coldboot race condition observed on emulators/simulatorsAnup Patel1-15/+29
If we are running on RISC-V emulator/simulator with large number of HARTs where each HART is a regular thread under UNIX host then it is possible that some of the secondary HARTs don't get chance to run and sbi_hart_wake_coldboot_harts() is called before secondary HARTs call sbi_hart_wait_for_coldboot(). In this situation, some of the secondary HARTs will never come-out of coldboot wait loop. To tackle this, we introduce a global flag coldboot_done which will be protected by coldboot lock and it will be set by primary HART from sbi_hart_wake_coldboot_harts() before waking-up secondary HARTs. We also re-arrange acquire/release of coldboot lock to reduce further chances of race-condition. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Nylon Chen<nylon7@andestech.com>
2019-09-30lib: Extend sbi_hart_switch_mode() to support hypervisor extensionAnup Patel1-2/+25
This patch extends sbi_hart_switch_mode() to support entering VS/VU modes when hypervisor extension is available. Signed-off-by: Anup Patel <anup.patel@wdc.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-30 09:37:43 +0300