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2019-12-16lib: Use MTINST CSR in misaligned load/store emulationAnup Patel1-8/+34
We should use MTINST CSR in misaligned load/store emulation whenever possible to avoid unpriv read in getting trapped instruction. This will improve preformance on HW having proper implementation of MTINST CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-12-16lib: Extend trap redirection for hypervisor v0.5 specAnup Patel4-25/+46
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-12-16lib: Fix sbi_get_insn() for load guest page faultAnup Patel1-0/+4
We should treat load guest page fault in sbi_get_insn() as fetch guest patch fault. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-12-16include: Extend struct sbi_trap_info for mtval2 and mtinstAnup Patel1-0/+6
We have two new trap CSRs namely mtval2 and mtinst when RISC-V hypervisor extension is available hence we extend struct sbi_trap_info accordingly. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-12-16lib: Delegate guest page faults to HS-modeAnup Patel1-6/+12
As-per RISC-V hypervisor v0.5 spec, we have new guest page faults which need to be delegated to HS-mode. Also, we can have bits in in MIDELEG and MEDELEG hardwired to 1 which means we need to fix the sainty check on these CSRs at the end of delegate_traps() function. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-11-27lib: Add error detection for misa_extensionXiang W1-1/+2
Add assertions for misa_extension to prevent incoming illegal characters. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-11-26lib: Fix probe extensionAtish Patra1-0/+1
The break statement is missing in base extension function handling. Fix the typo. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-11-26lib: Fix CPU capabilities detection functionXiang Wang2-2/+43
On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-11-21lib: Simplify trap parameters in sbi_ecall functionsAnup Patel1-25/+18
The out_tcause and out_tval parameters are not sufficient for most sbi_ecall functions because this will grow in-future when we support RISC-V hypervisor v0.5 draft. We replace these parameters with out_trap which is a pointer to struct sbi_trap_info. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-11-21lib: Better naming of unpriv APIs for wider useAnup Patel7-84/+114
The unpriv APIs can be useful to external firmware and out-of-tree platform support code. This patch adds "sbi_" prefix to unpriv load/store APIs and rename struct riscv_unpriv to struct sbi_trap_info everywhere. We also place struct sbi_trap_info in sbi/sbi_trap.h so that we can use it for sbi_trap_redirect() as well. Overall, this patch will make naming of unpriv APIs consistent with other OpenSBI APIs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-11-21lib: No need to set VSSTATUS.MXR bit in get_insn()Anup Patel3-26/+5
We don't need to set VSSTATUS.MXR bit in get_insn() for unpriv instruction read because MSTATUS.MXR bit applies to both "Stage1" and "Stage2" page tables. This also allows us to remove the "virt" parameter of get_insn() function. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-11-21include: Remove ilen member of struct unpriv_trapAnup Patel2-20/+32
We simplify struct unpriv_trap by removing ilen member. This can be achieved by ensuring that at all unpriv load/store instructions are 4 bytes long using GCC assembler option. Additionally, this also reduces few instructions from unpriv load/store functions. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-11-15lib: Remove date and time from init messageAlistair Francis1-4/+3
Building the date and time into the binary means the OpenSBI isn't reproducible. We don't really need the time so let's remove it. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-10-03lib: Provide a platform hook to implement vendor specific SBI extensions.Atish Patra1-3/+26
SBI v0.2 specification allows vendor extensions and it should be implemented in a independent of the core sbi library. Introduce a single platform callback that will let platforms handle all vendor extensions in platform specific code if they want. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-10-03lib: Implement SBI v0.2Atish Patra1-31/+125
SBI v0.2 introduces a base specification which is mandatory to implement for any SBI implementations that is not legacy. Add support for the base extension. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-10-03lib: Remove redundant variable assignmentAtish Patra1-10/+2
An ecall handler should only return error if valid SBI function fails. Otherwise, it should succeed with appropriate error in a0. Get rid of unnecessary setting of the temporary return variable to zero for the cases where errors are not expected. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-10-03lib: Rename existing SBI implementation as 0.1.Atish Patra1-18/+36
Current SBI implementation is now considered as version 0.1 and will be removed/replaced with newer extension/functions in future. Rename the existing implementations accordingly to be in sync with the specification. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Zong Li <zong.li@sifive.com>
2019-10-02lib: Fix coldboot race condition observed on emulators/simulatorsAnup Patel1-15/+29
If we are running on RISC-V emulator/simulator with large number of HARTs where each HART is a regular thread under UNIX host then it is possible that some of the secondary HARTs don't get chance to run and sbi_hart_wake_coldboot_harts() is called before secondary HARTs call sbi_hart_wait_for_coldboot(). In this situation, some of the secondary HARTs will never come-out of coldboot wait loop. To tackle this, we introduce a global flag coldboot_done which will be protected by coldboot lock and it will be set by primary HART from sbi_hart_wake_coldboot_harts() before waking-up secondary HARTs. We also re-arrange acquire/release of coldboot lock to reduce further chances of race-condition. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Nylon Chen<nylon7@andestech.com>
2019-09-30lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSRAnup Patel3-14/+108
For platforms not having TIME CSR, we trap-n-emulate TIME CSR read/write in OpenSBI. Same rationale applies to HTIMEDELTA CSR as well so we trap-n-emulate HTIMEDELTA CSR for platforms not having TIME CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-09-30include: Extend get_insn() to read instruction from VS/VU modeAnup Patel3-27/+46
Current implementation of get_insn() is not suitable for reading instruction from VS/VU mode because we have to set SSTATUS_MXR bit in VSSTATUS CSR for reading instruction from VS/VU mode. This patch extends get_insn() to read instruction from VS/VU mode. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2019-09-30lib: Redirect WFI trapped from VS/VU mode to HS-modeAnup Patel1-3/+17
The WFI will trap as illegal instruction trap when executed in VS/VU mode so we just forward/redirect it to HS-mode so that hypervisor can deal with it appropriately. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-09-30lib: Extend sbi_trap_redirect() for hypervisor extensionAnup Patel1-23/+102
When hypervisor extension is available, we can get traps from VS/VU modes. We should be able to force redirect some of these traps to HS-mode. In other words, we should be able forward traps from VS/VU mode to HS-mode using sbi_trap_redirect() hence this patch. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2019-09-30lib: Extend sbi_hart_switch_mode() to support hypervisor extensionAnup Patel2-4/+28
This patch extends sbi_hart_switch_mode() to support entering VS/VU modes when hypervisor extension is available. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-09-30lib: Delegate supervisor ecall to HS-mode when H extension availableAnup Patel1-0/+8
When hypervisor extension is available, we only handle hypervisor ecalls coming from HS-mode and we let hypervisor handle ecalls coming from VS-mode. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-09-28Write MSIP by using memory-mapped control registerZong Li1-1/+1
The machine-level MSIP bits are written by accesses to memory-mapped control registers. Only use CSR instruction for SSIP and USIP. There is no effect that using CSR instruction to write MSIP when testing on unleashed board and QEMU. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-09-10lib: provide a platform specific tlb range flush thresholdAtish Patra1-1/+4
Currently, the tlb range flush threshold is fixed and set to 4k for all platforms. However, it should be platform specific as it completely depends upon how platform actually implements sfence instruction. Define a platform feature that allows every individual platform to set different values. If a platform doesn't define it, just use a page size as the threshold. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-31lib: Upgrade to full flush if size is at least thresholdAtish Patra1-1/+1
Currently, we upgrade to a full tlb flush only If a tlb flush request size is greater than the threshold. This is done as sfence in RISC-V can only flush 4KB at a time. Doing a large number of flushes page by page impacts the performance. It is better to do a full tlbflush if the request size is at least equal to the threshold size. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-31lib: Support atomic swap instructionsAtish Patra1-18/+36
If compiler supports riscv atomic instructions, we should use them instead of legacy gcc built-in macros __sync_lock_test_and_set in atomic exchange functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-19Include `git describe` in OpenSBIPalmer Dabbelt1-0/+5
OpenSBI includes a version, but that is only updated when tagged. For users that are using the git releases we instead end up with an ambiguous version number, which makes it hard to figure out what everyone is using. This patch checks for a git directory and prints out the result of `git describe`, which is a mix of pretty and unambiguous. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-16lib: Fix race conditions in tlb fifo access.Atish Patra4-142/+251
Linux kernel expects tlb flush SBI call to be completely synchronous i.e. the SBI call should only return once corresponding *fence* instruction is executed. OpenSBI manages the outstanding TLB flush requests by keeping them in a per hart based fifo. However, there are few corner cases that may lead to race conditions while updating the fifo. Currently, the caller hart waits for IPI acknowledgement via clint address which is not a very good method as synchronization on MMIO may not be supported in every platform. Moreover, the waiter doesn't have any way of identifying if the IPI is received for specific tlb flush request or any other IPI. This may lead to unpredictable behavior in supervisor/user space. Fix this by waiting on individual fifo entries rather than MMIO address. Currently, a relaxed loop is being used because wfi again involves MMIO write which would be slower compared to relaxed loop. To avoid deadlock, fifo is processed every time a hart loops for fifo enqueue or fifo sync to consume the tlb flush requests sent by other harts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2019-08-16lib: Provide an atomic exchange function unsigned longAtish Patra1-0/+16
Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2019-08-13lib: Handle traps when doing unpriv load/store in get_insn()Anup Patel3-45/+63
We can get a page/access trap when doing unpriv load/store in get_insn() function because on a SMP system Linux swapper running on HART A can unmap pages from page table used by HART B. To tackle this we extend get_insn() implementation so that if we get trap in get_insn() then we redirect it to S-mode as fetch page/access fault. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-08-12lib: Correct null pointer checkJacob Garber1-1/+1
In order to prevent a possible null pointer dereference, return early if either one of 'in' or 'data' is null. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-08-12lib: Prevent unintended sign extensionsJacob Garber1-2/+4
In the last argument to sbi_memset() we essentially have the following multiplication: size_t = u16 * u16 Due to C's integer semantics, both u16's are implicitly converted to int before the multiplication, which cannot hold all possible values of a u16 * u16. If the multiplication overflows, the intermediate result will be a negative number. On 64-bit platforms, this will be sign-extended to a huge integer in the conversion to a u64 (aka size_t). Being the size argument to sbi_memset(), this could potentially cause a large out-of-bounds write. The solution is to manually cast one of the u16 to a size_t, which will make it large enough to avoid the implicit conversion and any overflow. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-08-12lib: Use bitwise & instead of boolean &&Jacob Garber1-1/+1
!(mipval && MIP_MSIP) simplifies to !mipval, which checks if the entire variable is zero, not just a single bit. Fix this to use bitwise & instead. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-08-09lib: Use sbi_dprintf() for invalid CSRsAnup Patel1-4/+4
We should sbi_dprintf() instead of sbi_printf() for invalid CSRs because we are forwarding invalid CSR access back to S-mode. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09lib: Introduce sbi_dprintf() APIAnup Patel1-0/+13
This patch introduces new sbi_dprintf() API for runtime debug prints. The sbi_dprintf() will print to console for a given HART only when SBI_SCRATCH_DEBUG_PRINTS option in enabled in sbi_scratch for this HART. We can now add debug prints using sbi_dprintf() at important places in OpenSBI sources. These debug prints will only show up when previous booting stage or compile time parameter sets the SBI_SCRATCH_DEBUG_PRINTS option in scratch space. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-26lib: Allow compiling without FP supportAnup Patel2-9/+14
Currently, we mandate 'F' and 'D' extension in riscv_fp.h so that misaligned load/store emulation has access to FP registers. The above is too restrictive and we should certainly allow compilation for soft-FP toolchains and explicit PLATFORM_RISCV_ISA not having 'F' and 'D' extensions. This patch extends riscv_fp.h and misaligned load/store emulation to allow compiling OpenSBI without FP support. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-19lib: Rename string.x to sbi_string.xAtish Patra6-37/+22
All string functions are part of libsbi. It makes more sense to rename them to sbi_string.x as the libsbi can be linked with external libraries that can have similar implementation. Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Anup Patel <anup.patel@wdc.com>
2019-06-19lib: Include helper libc functions directly in libsbi.Atish Patra6-6/+193
libsbi needs some of the custom libc functions. It should be directly included in libsbi instead of platform specific libraries. Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Anup Patel <anup.patel@wdc.com>
2019-06-19lib: Move sbi core library to lib/sbiAtish Patra20-0/+3323
Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Anup Patel <anup.patel@wdc.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-01 19:33:13 +0300