From 8050081f68b2b66f8937b15a6753ec6408c2fdee Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Tue, 17 Jan 2023 16:14:27 +0800 Subject: firmware: Not to clear all the MIP In generic behavior of QEMU, if the pending bits of PLIC are still set and we clear the SEIP, the QEMU may not set the SEIP back immediately and the interrupt may not be handled anymore until the new interrupts arrived and QEMU set the SEIP back which is a generic behavior in QEMU. Signed-off-by: Nick Hu Signed-off-by: Jim Shu Reviewed-by: Anup Patel --- firmware/fw_base.S | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/firmware/fw_base.S b/firmware/fw_base.S index fb6ac92..ceef44f 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -428,9 +428,15 @@ _start_warm: li ra, 0 call _reset_regs - /* Disable and clear all interrupts */ + /* Disable all interrupts */ csrw CSR_MIE, zero - csrw CSR_MIP, zero + /* + * Only clear the MIP_SSIP and MIP_STIP. For the platform like QEMU, + * If we clear other interrupts like MIP_SEIP and the pendings of + * PLIC still exist, the QEMU may not set it back immediately. + */ + li t0, (MIP_SSIP | MIP_STIP) + csrc CSR_MIP, t0 /* Find HART count and HART stack size */ lla a4, platform -- cgit v1.2.3