From aef9a60d521a7810557d1caf826311bc349691ac Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Sat, 9 May 2020 16:47:24 -0700 Subject: lib: Add csr detect support As RISC-V ISA allows many CSRs such as pmp, s/mcounteren to be optional in hardware, OpenSBI should provide an option to dynamically detect these csr access capability at run time. Implement a csr read/write access check helper macros. Signed-off-by: Atish Patra Tested-by: Jonathan Balkind Reviewed-by: Anup Patel --- include/sbi/sbi_csr_detect.h | 50 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/sbi/sbi_csr_detect.h diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h new file mode 100644 index 0000000..f294888 --- /dev/null +++ b/include/sbi/sbi_csr_detect.h @@ -0,0 +1,50 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __SBI_CSR_DETECT__H +#define __SBI_CSR_DETECT__H + +#include +#include + +#define csr_read_allowed(csr_num, trap) \ + ({ \ + register ulong tinfo asm("a3") = (ulong)trap; \ + register ulong ttmp asm("a4"); \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ + register ulong ret = 0; \ + asm volatile( \ + "add %[ttmp], %[tinfo], zero\n" \ + "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ + "csrr %[ret], %[csr]\n" \ + "csrw " STR(CSR_MTVEC) ", %[mtvec]" \ + : [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo), \ + [ttmp] "+&r"(ttmp), [ret] "=&r" (ret) \ + : [csr] "i" (csr_num) \ + : "memory"); \ + ret; \ + }) \ + +#define csr_write_allowed(csr_num, trap, value) \ + ({ \ + register ulong tinfo asm("a3") = (ulong)trap; \ + register ulong ttmp asm("a4"); \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ + asm volatile( \ + "add %[ttmp], %[tinfo], zero\n" \ + "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ + "csrw %[csr], %[val]\n" \ + "csrw " STR(CSR_MTVEC) ", %[mtvec]" \ + : [mtvec] "+&r"(mtvec), \ + [tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp) \ + : [csr] "i" (csr_num), [val] "r" (value) \ + : "memory"); \ + }) \ + +#endif -- cgit v1.2.3