From ec0d2a7d7d8b78193375651627aa6f65b9219afe Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Sat, 9 May 2020 16:47:30 -0700 Subject: lib: timer: Provide a hart based timer feature As per the RISC-V specification, time value can be obtained from a time CSR implemented in hardware or a MMIO based IP block. Qemu virt machine already supports timer csr while CLINT provides the timer for other platforms. Implement a hart specific timer feature that can be detected at runtime. As CSR based timer implementation are faster than MMIO address based, it is always preferred over MMIO based one. Signed-off-by: Atish Patra Tested-by: Jonathan Balkind Reviewed-by: Anup Patel --- include/sbi/sbi_hart.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/sbi/sbi_hart.h') diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index f7870d9..beb61b6 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -20,6 +20,8 @@ enum sbi_hart_features { SBI_HART_HAS_SCOUNTEREN = (1 << 1), /** Hart has M-mode counter enable */ SBI_HART_HAS_MCOUNTEREN = (1 << 2), + /** HART has timer csr implementation in hardware */ + SBI_HART_HAS_TIME = (1 << 3), }; struct sbi_scratch; -- cgit v1.2.3