From fde28fadc2603c7c7a4afa7c2e7b96cc7b11d2e2 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Sat, 10 Jul 2021 09:18:03 -0700 Subject: lib: sbi: Detect mcountinihibit support at runtime RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows software to stop any counter from incrementing. The SBI PMU extension depends on this CSR support in hardware. Define mcountinhibit as a hart specific feature and detect it at runtime. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- include/sbi/sbi_hart.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/sbi') diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 031c7b0..9e317c5 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -18,8 +18,10 @@ enum sbi_hart_features { SBI_HART_HAS_SCOUNTEREN = (1 << 0), /** Hart has M-mode counter enable */ SBI_HART_HAS_MCOUNTEREN = (1 << 1), + /** Hart has counter inhibit CSR */ + SBI_HART_HAS_MCOUNTINHIBIT = (1 << 2), /** HART has timer csr implementation in hardware */ - SBI_HART_HAS_TIME = (1 << 2), + SBI_HART_HAS_TIME = (1 << 3), /** Last index of Hart features*/ SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME, -- cgit v1.2.3