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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2019 FORTH-ICS/CARV
* Panagiotis Peristerakis <perister@ics.forth.gr>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/ipi/aclint_mswi.h>
#include <sbi_utils/irqchip/plic.h>
#include <sbi_utils/serial/uart8250.h>
#include <sbi_utils/timer/aclint_mtimer.h>
#define ARIANE_UART_ADDR 0x10000000
#define ARIANE_UART_FREQ 50000000
#define ARIANE_UART_BAUDRATE 115200
#define ARIANE_UART_REG_SHIFT 2
#define ARIANE_UART_REG_WIDTH 4
#define ARIANE_UART_REG_OFFSET 0
#define ARIANE_PLIC_ADDR 0xc000000
#define ARIANE_PLIC_NUM_SOURCES 3
#define ARIANE_HART_COUNT 1
#define ARIANE_CLINT_ADDR 0x2000000
#define ARIANE_ACLINT_MTIMER_FREQ 1000000
#define ARIANE_ACLINT_MSWI_ADDR (ARIANE_CLINT_ADDR + \
CLINT_MSWI_OFFSET)
#define ARIANE_ACLINT_MTIMER_ADDR (ARIANE_CLINT_ADDR + \
CLINT_MTIMER_OFFSET)
static struct plic_data plic = {
.addr = ARIANE_PLIC_ADDR,
.num_src = ARIANE_PLIC_NUM_SOURCES,
};
static struct aclint_mswi_data mswi = {
.addr = ARIANE_ACLINT_MSWI_ADDR,
.size = ACLINT_MSWI_SIZE,
.first_hartid = 0,
.hart_count = ARIANE_HART_COUNT,
};
static struct aclint_mtimer_data mtimer = {
.mtime_freq = ARIANE_ACLINT_MTIMER_FREQ,
.mtime_addr = ARIANE_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIME_OFFSET,
.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
.mtimecmp_addr = ARIANE_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIMECMP_OFFSET,
.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
.first_hartid = 0,
.hart_count = ARIANE_HART_COUNT,
.has_64bit_mmio = TRUE,
};
/*
* Ariane platform early initialization.
*/
static int ariane_early_init(bool cold_boot)
{
/* For now nothing to do. */
return 0;
}
/*
* Ariane platform final initialization.
*/
static int ariane_final_init(bool cold_boot)
{
void *fdt;
if (!cold_boot)
return 0;
fdt = fdt_get_address();
fdt_fixups(fdt);
return 0;
}
/*
* Initialize the ariane console.
*/
static int ariane_console_init(void)
{
return uart8250_init(ARIANE_UART_ADDR,
ARIANE_UART_FREQ,
ARIANE_UART_BAUDRATE,
ARIANE_UART_REG_SHIFT,
ARIANE_UART_REG_WIDTH,
ARIANE_UART_REG_OFFSET);
}
static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
if (ret)
return ret;
}
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
if (ret)
return ret;
}
return 0;
}
/*
* Initialize the ariane interrupt controller for current HART.
*/
static int ariane_irqchip_init(bool cold_boot)
{
u32 hartid = current_hartid();
int ret;
if (cold_boot) {
ret = plic_cold_irqchip_init(&plic);
if (ret)
return ret;
}
return plic_ariane_warm_irqchip_init(2 * hartid, 2 * hartid + 1);
}
/*
* Initialize IPI for current HART.
*/
static int ariane_ipi_init(bool cold_boot)
{
int ret;
if (cold_boot) {
ret = aclint_mswi_cold_init(&mswi);
if (ret)
return ret;
}
return aclint_mswi_warm_init();
}
/*
* Initialize ariane timer for current HART.
*/
static int ariane_timer_init(bool cold_boot)
{
int ret;
if (cold_boot) {
ret = aclint_mtimer_cold_init(&mtimer, NULL);
if (ret)
return ret;
}
return aclint_mtimer_warm_init();
}
/*
* Platform descriptor.
*/
const struct sbi_platform_operations platform_ops = {
.early_init = ariane_early_init,
.final_init = ariane_final_init,
.console_init = ariane_console_init,
.irqchip_init = ariane_irqchip_init,
.ipi_init = ariane_ipi_init,
.timer_init = ariane_timer_init,
};
const struct sbi_platform platform = {
.opensbi_version = OPENSBI_VERSION,
.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
.name = "ARIANE RISC-V",
.features = SBI_PLATFORM_DEFAULT_FEATURES,
.hart_count = ARIANE_HART_COUNT,
.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
.platform_ops_addr = (unsigned long)&platform_ops
};
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