diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2017-10-26 14:23:19 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-11-17 15:44:13 +0300 |
| commit | 1543bf794f4cf863b4c70eb9debba5fc1d2ebd6b (patch) | |
| tree | e274e317b778b67e276832726a2c5de4284c8240 | |
| parent | 5829fe2d59d8c088dadc43dedb36a657d791970c (diff) | |
| download | u-boot-1543bf794f4cf863b4c70eb9debba5fc1d2ebd6b.tar.xz | |
clk: clk_stm32f7: fix PLL clock division factor
Fix clock division factor initialization for RCC_PLLCFGR
registers.
PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/clk_stm32f7.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index a273f8ff5e..f1a9e9ca44 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -136,13 +136,15 @@ static int configure_clocks(struct udevice *dev) | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); /* Configure the main PLL */ - uint32_t pllcfgr = 0; - pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ - pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; - pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; - pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; - pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; - writel(pllcfgr, ®s->pllcfgr); + setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, + sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT); + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, + sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT); + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, + ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, + sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT); /* Enable the main PLL */ setbits_le32(®s->cr, RCC_CR_PLLON); |