diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2020-03-26 13:33:36 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-04-04 17:08:44 +0300 |
| commit | 4d073fa83bed62c65aeedb71c4b5584371dc59b7 (patch) | |
| tree | c2d8105effc25c191654e7ef8afab5b84a7f1207 | |
| parent | d0f7ab531057d666ebebeb8bb1860f52010e7a84 (diff) | |
| download | u-boot-4d073fa83bed62c65aeedb71c4b5584371dc59b7.tar.xz | |
x86: acpi: Describe USB 3 host controller found on Intel Tangier
USB 3 host controller may be described in ACPI to allow users alter
the properties or other features. Describe it for Intel Tangier SoC.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/include/asm/arch-tangier/acpi/southcluster.asl | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 6ccdc25136..f088fe3cf5 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -321,6 +321,53 @@ Device (PCI0) } } + Device (DWC3) + { + Name (_ADR, 0x00110000) + Name (_DEP, Package () + { + ^IPC1.PMIC + }) + + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Device (RHUB) + { + Name (_ADR, Zero) + + /* GPLD: Generate Port Location Data (PLD) */ + Method (GPLD, 1, Serialized) { + Name (PCKG, Package () { + Buffer (0x14) {} + }) + + /* REV: Revision 0x02 for ACPI 5.0 */ + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x0002, REV) + + /* VISI: Port visibility to user per port */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + /* VOFF: Vertical offset is not supplied */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x80, 0x10, VOFF) + Store (0xFFFF, VOFF) + + /* HOFF: Horizontal offset is not supplied */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x90, 0x10, HOFF) + Store (0xFFFF, HOFF) + + Return (PCKG) + } + + Device (HS01) { Name (_ADR, 1) } + Device (SS01) { Name (_ADR, 2) } + } + } + Device (PWM0) { Name (_ADR, 0x00170000) |