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author | Samin Guo <samin.guo@starfivetech.com> | 2022-11-01 11:19:48 +0300 |
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committer | Samin Guo <samin.guo@starfivetech.com> | 2022-11-01 13:54:30 +0300 |
commit | 0dbe3fb0be546f2be7adaee6baf6d550fbba4e26 (patch) | |
tree | 7f1d5836620b8522a4317dd5627d5fcc5a23973f | |
parent | bd7deb0588459f36cf774ed58a419a7efbc9d5e4 (diff) | |
download | u-boot-0dbe3fb0be546f2be7adaee6baf6d550fbba4e26.tar.xz |
board:starfive:evb: add get_chip_type
Read the chip model from the rgpio3 and setenv "chip_vision"
1: jh7110B
0: JH7110A
defalut: JH7110A
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
-rw-r--r-- | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 2 | ||||
-rw-r--r-- | board/starfive/evb/starfive_evb.c | 28 |
2 files changed, 29 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index 6a2b67bb3c..ad04e8877c 100644 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -15,6 +15,7 @@ #define AON_SYSCON_BASE 0x17010000 #define SYS_CRG_BASE 0x13020000 #define AON_CRG_BASE 0x17000000 +#define AON_IOMUX_BASE 0x17020000 #define STG_CRG_BASE 0x10230000 #define CLK_ENABLE_MASK 0x80000000U #define SYS_CRG_RESET_ASSERT3_SHIFT 0X304U @@ -75,6 +76,7 @@ #define PCIE_USB3_RX_STANDBY_MASK 0x80U #define PCIE_USB3_PHY_ENABLE_SHIFT 0x4U #define PCIE_USB3_PHY_ENABLE_MASK 0x10U +#define AON_GPIO_DIN_REG 0x2c /*timer cfg*/ #define TIMER_CLK_APB_SHIFT 0x1F0U diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c index 63fa24e3b1..9955c97b9b 100644 --- a/board/starfive/evb/starfive_evb.c +++ b/board/starfive/evb/starfive_evb.c @@ -17,6 +17,12 @@ #include <linux/bitops.h> #include <asm/arch/gpio.h> +enum chip_type_t { + CHIP_A = 0, + CHIP_B, + CHIP_MAX, +}; + #define SYS_CLOCK_ENABLE(clk) \ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) @@ -157,6 +163,26 @@ static void jh7110_usb_init(bool usb2_enable) } +static u32 get_chip_type(void) +{ + u32 value; + + value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG); + value = (value & BIT(3)) >> 3; + switch (value) { + case CHIP_B: + env_set("chip_vision", "B"); + jh7110_gmac_sel_tx_to_rgmii(0); + jh7110_gmac_sel_tx_to_rgmii(1); + break; + case CHIP_A: + default: + env_set("chip_vision", "A"); + break; + } + return value; +} + static void jh7110_mmc_init(int id) { if (id == 0) { @@ -238,7 +264,7 @@ err: #endif eth_env_set_enetaddr("eth0addr", mac0); eth_env_set_enetaddr("eth1addr", mac1); - + get_chip_type(); return 0; } #endif |