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| author | andy.hu <andy.hu@starfivetech.com> | 2023-03-17 13:08:54 +0300 |
|---|---|---|
| committer | andy.hu <andy.hu@starfivetech.com> | 2023-03-17 13:08:54 +0300 |
| commit | 4dd49f9bdc9eeb524671087c06de8a871f19e0f4 (patch) | |
| tree | 1d130b913d7e897e4cf07044af6278a4ee597187 | |
| parent | 6d6509830845b9f3c2752519726b443454795a76 (diff) | |
| parent | 0908b45ec975444ac624086959b090f789ea7b56 (diff) | |
| download | u-boot-4dd49f9bdc9eeb524671087c06de8a871f19e0f4.tar.xz | |
Merge branch 'CR_4082_apply_csr_patch_Andy.Hu' into 'jh7110-master'
CR_4082: riscv: Fix build against binutils 2.38
See merge request sdk/u-boot!43
| -rw-r--r-- | arch/riscv/Kconfig | 15 | ||||
| -rw-r--r-- | arch/riscv/Makefile | 24 |
2 files changed, 36 insertions, 3 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b0aa8d2ab9..2cff0d9536 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -161,6 +161,21 @@ config RISCV_ISA_C when building U-Boot, which results in compressed instructions in the U-Boot binary. +config RISCV_ISA_F + bool "Standard extension for Single-Precision Floating Point" + default y + help + Adds "F" to the ISA string passed to the compiler. + +config RISCV_ISA_D + bool "Standard extension for Double-Precision Floating Point" + depends on RISCV_ISA_F + default y + help + Adds "D" to the ISA string passed to the compiler and changes the + riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to + lp64d. + config RISCV_ISA_A def_bool y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d86..4963b5109b 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,15 +5,22 @@ ifeq ($(CONFIG_ARCH_RV64I),y) ARCH_BASE = rv64im - ABI = lp64 + ABI_BASE = lp64 endif ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im - ABI = ilp32 + ABI_BASE = ilp32 endif ifeq ($(CONFIG_RISCV_ISA_A),y) ARCH_A = a endif +ifeq ($(CONFIG_RISCV_ISA_F),y) + ARCH_F = f +endif +ifeq ($(CONFIG_RISCV_ISA_D),y) + ARCH_D = d + ABI_D = d +endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif @@ -24,7 +31,18 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ + +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) +ABI = $(ABI_BASE)$(ABI_D) + +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) +ifeq ($(toolchain-need-zicsr-zifencei),y) + RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei +endif + +ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) |