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author | William Qiu <william.qiu@starfivetech.com> | 2023-07-28 13:25:21 +0300 |
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committer | William Qiu <william.qiu@starfivetech.com> | 2023-07-28 13:25:21 +0300 |
commit | 7818499b71d2b5404ddf4b62bf1106710168af9a (patch) | |
tree | 6d2a1ab0dc338005df394ccf37f9d09c4fa21b73 | |
parent | 3b5813075cd43556a7bef86f53ce5be7193ba4c9 (diff) | |
download | u-boot-7818499b71d2b5404ddf4b62bf1106710168af9a.tar.xz |
riscv: dts: starfive: limit cclk_in frequency
The frequency of cclk_in is limited to 50M, so that it does not do internal
part frequency and goes by-pass mode. And delete syscon node.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
-rw-r--r-- | arch/riscv/dts/starfive_evb.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts index 6f865f7094..19b8e5f1e0 100644 --- a/arch/riscv/dts/starfive_evb.dts +++ b/arch/riscv/dts/starfive_evb.dts @@ -246,6 +246,8 @@ }; &sdio0 { + assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>; + assigned-clock-rates = <50000000>; fifo-depth = <32>; bus-width = <4>; status = "okay"; |