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author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-04-13 10:08:47 +0300 |
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committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:34 +0300 |
commit | ef888a4df1dd200a95e8eb7aa90d0b08b89a1964 (patch) | |
tree | 4805e0d21889a1d8c64945c4f5bad404a0869cc4 | |
parent | e9cef6c8ce31ff51099f23e2d628483cf762d728 (diff) | |
download | u-boot-ef888a4df1dd200a95e8eb7aa90d0b08b89a1964.tar.xz |
riscv:soc:jh7110: Add support jh7110 soc.
Add StarFive JH7110 soc to support RISC-V arch
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
-rw-r--r-- | arch/riscv/Kconfig | 1 | ||||
-rw-r--r-- | arch/riscv/cpu/jh7110/Kconfig | 50 | ||||
-rw-r--r-- | arch/riscv/cpu/jh7110/Makefile | 10 | ||||
-rw-r--r-- | arch/riscv/cpu/jh7110/cpu.c | 22 | ||||
-rw-r--r-- | arch/riscv/cpu/jh7110/dram.c | 38 | ||||
-rw-r--r-- | arch/riscv/cpu/jh7110/spl.c | 45 | ||||
-rw-r--r-- | arch/riscv/include/asm/arch-jh7110/spl.h | 14 |
7 files changed, 180 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ec651fe0a4..52e99e03d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -71,6 +71,7 @@ source "arch/riscv/cpu/ax25/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/jh7110/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 0000000000..6755696b4f --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive, Inc + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SPL_SIFIVE_CLINT + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + imply SMP + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply MII + imply MMC + imply MMC_SPI + imply MMC_BROKEN_CD + imply CMD_MMC + imply DM_GPIO + imply STARFIVE_GPIO + imply CMD_GPIO + imply MISC + imply STARFIVE_OTP + imply DM_PWM + imply DM_I2C + imply SYS_I2C_OCORES + imply CLK_JH7110 + +choice + prompt "JH7110 GMAC Speed" + depends on STARFIVE_JH7110 + default FPGA_GMAC_SPEED10 + help + choice JH7110 GMAC speed. + (GMAC only works well on 10M/duple, for FPGA board.) + + config FPGA_GMAC_SPEED10 + bool "GMAC works on 10M mode" + config FPGA_GMAC_SPEED100 + bool "GMAC works on 100M mode" + config FPGA_GMAC_SPEED_AUTO + bool "GMAC works on auto mode" + +endchoice diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile new file mode 100644 index 0000000000..1d13975876 --- /dev/null +++ b/arch/riscv/cpu/jh7110/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive, Inc + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += spl.o +else +obj-y += dram.o +obj-y += cpu.o +endif diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c new file mode 100644 index 0000000000..f13c18942f --- /dev/null +++ b/arch/riscv/cpu/jh7110/cpu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <irq_func.h> +#include <asm/cache.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c new file mode 100644 index 0000000000..1dc77efeca --- /dev/null +++ b/arch/riscv/cpu/jh7110/dram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +ulong board_get_usable_ram_top(ulong total_size) +{ +#ifdef CONFIG_64BIT + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (gd->ram_top > SZ_4G) + return SZ_4G; +#endif + return gd->ram_top; +} diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c new file mode 100644 index 0000000000..cb6ef2fda5 --- /dev/null +++ b/arch/riscv/cpu/jh7110/spl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <dm.h> +#include <log.h> +#include <asm/csr.h> + +#define CSR_U74_FEATURE_DISABLE 0x7c1 + +int spl_soc_init(void) +{ + int ret; + struct udevice *dev; + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + /*flash init*/ + ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev); + if (ret) { + debug("SPI init failed: %d\n", ret); + return ret; + } + return 0; +} + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +} diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h new file mode 100644 index 0000000000..0756020809 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#ifndef _SPL_STARFIVE_H +#define _SPL_STARFIVE_H + +int spl_soc_init(void); + +#endif /* _SPL_STARFIVE_H */ + |