diff options
author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-03-18 13:21:46 +0300 |
---|---|---|
committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:33 +0300 |
commit | 56c86383dc88850ee2e5af197532939b861f573b (patch) | |
tree | ae0aa6c916c5ca4933784069f84f468ce77e8928 | |
parent | d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 (diff) | |
download | u-boot-56c86383dc88850ee2e5af197532939b861f573b.tar.xz |
Reset:Starfive-jh7110: Add reset driver for JH7110
Support for reset controller on starfive JH7110 SoCs.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
-rw-r--r-- | drivers/reset/Kconfig | 8 | ||||
-rw-r--r-- | drivers/reset/Makefile | 1 | ||||
-rw-r--r-- | drivers/reset/reset-jh7110.c | 244 | ||||
-rw-r--r-- | include/dt-bindings/reset/starfive-jh7110.h | 219 |
4 files changed, 472 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d73daf5e31..6c92a10a93 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -164,6 +164,14 @@ config RESET_IPQ419 Support for reset controller on Qualcomm IPQ40xx SoCs. +config RESET_JH7110 + bool "Reset driver for Starfive JH7110 SoC" + depends on DM_RESET && TARGET_STARFIVE_VISIONFIVE + default y + help + Support for reset controller on Starfive + JH7110 SoCs. + config RESET_SIFIVE bool "Reset Driver for SiFive SoC's" depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index d69486bdeb..02c2812b0b 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o +obj-$(CONFIG_RESET_JH7110) += reset-jh7110.o diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c new file mode 100644 index 0000000000..79d5c5cbb0 --- /dev/null +++ b/drivers/reset/reset-jh7110.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: samin <samin.guo@starfivetech.com> + * yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <malloc.h> +#include <reset-uclass.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <dt-bindings/reset/starfive-jh7110.h> + +#define AONCRG_RESET_ASSERT 0x38 +#define AONCRG_RESET_STATUS 0x3C +#define ISPCRG_RESET_ASSERT 0x38 +#define ISPCRG_RESET_STATUS 0x3C +#define VOUTCRG_RESET_ASSERT 0x48 +#define VOUTCRG_RESET_STATUS 0x4C +#define STGCRG_RESET_ASSERT 0x74 +#define STGCRG_RESET_STATUS 0x78 +#define SYSCRG_RESET_ASSERT0 0x2F8 +#define SYSCRG_RESET_ASSERT1 0x2FC +#define SYSCRG_RESET_ASSERT2 0x300 +#define SYSCRG_RESET_ASSERT3 0x304 +#define SYSCRG_RESET_STATUS0 0x308 +#define SYSCRG_RESET_STATUS1 0x30C +#define SYSCRG_RESET_STATUS2 0x310 +#define SYSCRG_RESET_STATUS3 0x314 + +struct reset_assert_t { + void __iomem *assert; + void __iomem *status; +}; + +enum JH7110_RESET_CRG_GROUP { + SYSCRG_0 = 0, + SYSCRG_1, + SYSCRG_2, + SYSCRG_3, + STGCRG, + AONCRG, + ISPCRG, + VOUTCRG, +}; + +struct jh7110_reset_priv { + void __iomem *syscrg; + void __iomem *stgcrg; + void __iomem *aoncrg; + void __iomem *ispcrg; + void __iomem *voutcrg; +}; + +static const u32 jh7110_reset_asserted[8] = { + /* SYSCRG_STATUS0 */ + BIT(RSTN_U0_U7MC_RST_BUS % 32) | + BIT(RSTN_U0_U7MC_CORE0 % 32) | + BIT(RSTN_U0_U7MC_CORE1 % 32) | + BIT(RSTN_U0_U7MC_CORE2 % 32) | + BIT(RSTN_U0_U7MC_CORE3 % 32) | + BIT(RSTN_U0_U7MC_CORE4 % 32), + /* SYSCRG_STATUS1 */ + 0, + /* SYSCRG_STATUS2 */ + 0, + /* SYSCRG_STATUS3 */ + 0, + /* STGCRG */ + BIT(RSTN_U0_HIFI4_CORE % 32) | + BIT(RSTN_U0_E24_CORE % 32), + /* AONCRG */ + 0, + /* ISPCRG */ + 0, + /*VOUTCRG*/ + 0, +}; + +static int jh7110_get_reset(struct jh7110_reset_priv *priv, + struct reset_assert_t *reset, + unsigned long group) +{ + switch (group) { + case SYSCRG_0: + reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT0; + reset->status = priv->syscrg + SYSCRG_RESET_STATUS0; + break; + case SYSCRG_1: + reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT1; + reset->status = priv->syscrg + SYSCRG_RESET_STATUS1; + break; + case SYSCRG_2: + reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT2; + reset->status = priv->syscrg + SYSCRG_RESET_STATUS2; + break; + case SYSCRG_3: + reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT3; + reset->status = priv->syscrg + SYSCRG_RESET_STATUS3; + break; + case STGCRG: + reset->assert = priv->stgcrg + STGCRG_RESET_ASSERT; + reset->status = priv->stgcrg + STGCRG_RESET_STATUS; + break; + case AONCRG: + reset->assert = priv->aoncrg + AONCRG_RESET_ASSERT; + reset->status = priv->aoncrg + AONCRG_RESET_STATUS; + break; + + case ISPCRG: + reset->assert = priv->ispcrg + ISPCRG_RESET_ASSERT; + reset->status = priv->ispcrg + ISPCRG_RESET_STATUS; + break; + case VOUTCRG: + reset->assert = priv->voutcrg + VOUTCRG_RESET_ASSERT; + reset->status = priv->voutcrg + VOUTCRG_RESET_STATUS; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int jh7110_reset_trigger(struct jh7110_reset_priv *priv, + unsigned long id, bool assert) +{ + struct reset_assert_t reset; + unsigned long group; + u32 mask, value, done; + int ret; + + group = id / 32; + mask = BIT(id % 32); + ret = jh7110_get_reset(priv, &reset, group); + if (ret) { + debug("reset: bad reset id.\n"); + return ret; + } + + done = jh7110_reset_asserted[group] & mask; + + if (!assert) + done ^= mask; + + value = readl(reset.assert); + if (assert) + value |= mask; + else + value &= ~mask; + writel(value, reset.assert); + + /* if the associated clock is gated, deasserting might otherwise hang forever */ + ret = readl_poll_timeout(reset.status, value, (value & mask) == done, 100000); + if (ret) + debug("reset %ld: timeout.\n", id); + + return ret; +} + +static int jh7110_reset_assert(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + jh7110_reset_trigger(priv, rst->id, true); + + return 0; +} + +static int jh7110_reset_deassert(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + jh7110_reset_trigger(priv, rst->id, false); + + return 0; +} + +static int jh7110_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int jh7110_reset_request(struct reset_ctl *rst) +{ + if (rst->id >= RSTN_JH7110_RESET_END) + return -EINVAL; + + return 0; +} + +struct reset_ops jh7110_reset_reset_ops = { + .rfree = jh7110_reset_free, + .request = jh7110_reset_request, + .rst_assert = jh7110_reset_assert, + .rst_deassert = jh7110_reset_deassert, +}; + +static const struct udevice_id jh7110_reset_ids[] = { + { .compatible = "starfive,jh7110-reset" }, + { /* sentinel */ } +}; + +static int jh7110_reset_probe(struct udevice *dev) +{ + struct jh7110_reset_priv *priv = dev_get_priv(dev); + + priv->syscrg = dev_remap_addr_name(dev, "syscrg"); + if (!priv->syscrg) + return -EINVAL; + + priv->stgcrg = dev_remap_addr_name(dev, "stgcrg"); + if (!priv->stgcrg) + return -EINVAL; + + priv->aoncrg = dev_remap_addr_name(dev, "aoncrg"); + if (!priv->aoncrg) + return -EINVAL; + + priv->ispcrg = dev_remap_addr_name(dev, "ispcrg"); + if (!priv->ispcrg) + return -EINVAL; + + priv->voutcrg = dev_remap_addr_name(dev, "voutcrg"); + if (!priv->voutcrg) + return -EINVAL; + + return 0; +} + +U_BOOT_DRIVER(jh7110_reset) = { + .name = "jh7110-reset", + .id = UCLASS_RESET, + .of_match = jh7110_reset_ids, + .ops = &jh7110_reset_reset_ops, + .probe = jh7110_reset_probe, + .priv_auto = sizeof(struct jh7110_reset_priv), +}; diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h new file mode 100644 index 0000000000..5a4d973584 --- /dev/null +++ b/include/dt-bindings/reset/starfive-jh7110.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: samin <samin.guo@starfivetech.com> + * yanhong <yanhong.wang@starfivetech.com> + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ + +/* + * group[0]: syscrg: assert0 + */ +#define RSTN_U0_JTAG2APB_PRESETN 0 +#define RSTN_U0_SYS_SYSCON_PRESETN 1 +#define RSTN_U0_SYS_IOMUX_PRESETN 2 +#define RSTN_U0_U7MC_RST_BUS 3 +#define RSTN_U0_U7MC_DEBUG 4 +#define RSTN_U0_U7MC_CORE0 5 +#define RSTN_U0_U7MC_CORE1 6 +#define RSTN_U0_U7MC_CORE2 7 +#define RSTN_U0_U7MC_CORE3 8 +#define RSTN_U0_U7MC_CORE4 9 +#define RSTN_U0_U7MC_CORE0_ST 10 +#define RSTN_U0_U7MC_CORE1_ST 11 +#define RSTN_U0_U7MC_CORE2_ST 12 +#define RSTN_U0_U7MC_CORE3_ST 13 +#define RSTN_U0_U7MC_CORE4_ST 14 +#define RSTN_U0_U7MC_TRACE_RST0 15 +#define RSTN_U0_U7MC_TRACE_RST1 16 +#define RSTN_U0_U7MC_TRACE_RST2 17 +#define RSTN_U0_U7MC_TRACE_RST3 18 +#define RSTN_U0_U7MC_TRACE_RST4 19 +#define RSTN_U0_U7MC_TRACE_COM 20 +#define RSTN_U0_IMG_GPU_APB 21 +#define RSTN_U0_IMG_GPU_DOMA 22 +#define RSTN_U0_NOC_BUS_APB_BUS_N 23 +#define RSTN_U0_NOC_BUS_AXICFG0_AXI_N 24 +#define RSTN_U0_NOC_BUS_CPU_AXI_N 25 +#define RSTN_U0_NOC_BUS_DISP_AXI_N 26 +#define RSTN_U0_NOC_BUS_GPU_AXI_N 27 +#define RSTN_U0_NOC_BUS_ISP_AXI_N 28 +#define RSTN_U0_NOC_BUS_DDRC_N 29 +#define RSTN_U0_NOC_BUS_STG_AXI_N 30 +#define RSTN_U0_NOC_BUS_VDEC_AXI_N 31 +/* + * group[1]: syscrg: assert1 + */ +#define RSTN_U0_NOC_BUS_VENC_AXI_N 32 +#define RSTN_U0_AXI_CFG1_DEC_AHB 33 +#define RSTN_U0_AXI_CFG1_DEC_MAIN 34 +#define RSTN_U0_AXI_CFG0_DEC_MAIN 35 +#define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV 36 +#define RSTN_U0_AXI_CFG0_DEC_HIFI4 37 +#define RSTN_U0_DDR_AXI 38 +#define RSTN_U0_DDR_OSC 39 +#define RSTN_U0_DDR_APB 40 +#define RSTN_U0_DOM_ISP_TOP_N 41 +#define RSTN_U0_DOM_ISP_TOP_AXI 42 +#define RSTN_U0_DOM_VOUT_TOP_SRC 43 +#define RSTN_U0_CODAJ12_AXI 44 +#define RSTN_U0_CODAJ12_CORE 45 +#define RSTN_U0_CODAJ12_APB 46 +#define RSTN_U0_WAVE511_AXI 47 +#define RSTN_U0_WAVE511_BPU 48 +#define RSTN_U0_WAVE511_VCE 49 +#define RSTN_U0_WAVE511_APB 50 +#define RSTN_U0_VDEC_JPG_ARB_JPG 51 +#define RSTN_U0_VDEC_JPG_ARB_MAIN 52 +#define RSTN_U0_AXIMEM_128B_AXI 53 +#define RSTN_U0_WAVE420L_AXI 54 +#define RSTN_U0_WAVE420L_BPU 55 +#define RSTN_U0_WAVE420L_VCE 56 +#define RSTN_U0_WAVE420L_APB 57 +#define RSTN_U1_AXIMEM_128B_AXI 58 +#define RSTN_U2_AXIMEM_128B_AXI 59 +#define RSTN_U0_INTMEM_ROM_SRAM_ROM 60 +#define RSTN_U0_CDNS_QSPI_AHB 61 +#define RSTN_U0_CDNS_QSPI_APB 62 +#define RSTN_U0_CDNS_QSPI_REF 63 +/* + * group[2]: syscrg: assert2 + */ +#define RSTN_U0_DW_SDIO_AHB 64 +#define RSTN_U1_DW_SDIO_AHB 65 +#define RSTN_U1_DW_GMAC5_AXI64_A_I 66 +#define RSTN_U1_DW_GMAC5_AXI64_H_N 67 +#define RSTN_U0_MAILBOX_RRESETN 68 +#define RSTN_U0_SSP_SPI_APB 69 +#define RSTN_U1_SSP_SPI_APB 70 +#define RSTN_U2_SSP_SPI_APB 71 +#define RSTN_U3_SSP_SPI_APB 72 +#define RSTN_U4_SSP_SPI_APB 73 +#define RSTN_U5_SSP_SPI_APB 74 +#define RSTN_U6_SSP_SPI_APB 75 +#define RSTN_U0_DW_I2C_APB 76 +#define RSTN_U1_DW_I2C_APB 77 +#define RSTN_U2_DW_I2C_APB 78 +#define RSTN_U3_DW_I2C_APB 79 +#define RSTN_U4_DW_I2C_APB 80 +#define RSTN_U5_DW_I2C_APB 81 +#define RSTN_U6_DW_I2C_APB 82 +#define RSTN_U0_DW_UART_APB 83 +#define RSTN_U0_DW_UART_CORE 84 +#define RSTN_U1_DW_UART_APB 85 +#define RSTN_U1_DW_UART_CORE 86 +#define RSTN_U2_DW_UART_APB 87 +#define RSTN_U2_DW_UART_CORE 88 +#define RSTN_U3_DW_UART_APB 89 +#define RSTN_U3_DW_UART_CORE 90 +#define RSTN_U4_DW_UART_APB 91 +#define RSTN_U4_DW_UART_CORE 92 +#define RSTN_U5_DW_UART_APB 93 +#define RSTN_U5_DW_UART_CORE 94 +#define RSTN_U0_CDNS_SPDIF_APB 95 +/* + * group[3]: syscrg: assert3 + */ +#define RSTN_U0_PWMDAC_APB 96 +#define RSTN_U0_PDM_4MIC_DMIC 97 +#define RSTN_U0_PDM_4MIC_APB 98 +#define RSTN_U0_I2SRX_3CH_APB 99 +#define RSTN_U0_I2SRX_3CH_BCLK 100 +#define RSTN_U0_I2STX_4CH_APB 101 +#define RSTN_U0_I2STX_4CH_BCLK 102 +#define RSTN_U1_I2STX_4CH_APB 103 +#define RSTN_U1_I2STX_4CH_BCLK 104 +#define RSTN_U0_TDM16SLOT_AHB 105 +#define RSTN_U0_TDM16SLOT_TDM 106 +#define RSTN_U0_TDM16SLOT_APB 107 +#define RSTN_U0_PWM_8CH_APB 108 +#define RSTN_U0_DSKIT_WDT_APB 109 +#define RSTN_U0_DSKIT_WDT_CORE 110 +#define RSTN_U0_CAN_CTRL_APB 111 +#define RSTN_U0_CAN_CTRL_CORE 112 +#define RSTN_U0_CAN_CTRL_TIMER 113 +#define RSTN_U1_CAN_CTRL_APB 114 +#define RSTN_U1_CAN_CTRL_CORE 115 +#define RSTN_U1_CAN_CTRL_TIMER 116 +#define RSTN_U0_SI5_TIMER_APB 117 +#define RSTN_U0_SI5_TIMER_TIMER0 118 +#define RSTN_U0_SI5_TIMER_TIMER1 119 +#define RSTN_U0_SI5_TIMER_TIMER2 120 +#define RSTN_U0_SI5_TIMER_TIMER3 121 +#define RSTN_U0_INT_CTRL_APB 122 +#define RSTN_U0_TEMP_SENSOR_APB 123 +#define RSTN_U0_TEMP_SENSOR_TEMP 124 +#define RSTN_U0_JTAG_CERTIFICATION_N 125 +/* + * group[4]: stgcrg + */ +#define RSTN_U0_STG_SYSCON_PRESETN 128 +#define RSTN_U0_HIFI4_CORE 129 +#define RSTN_U0_HIFI4_AXI 130 +#define RSTN_U0_SEC_TOP_HRESETN 131 +#define RSTN_U0_E24_CORE 132 +#define RSTN_U0_DW_DMA1P_AXI 133 +#define RSTN_U0_DW_DMA1P_AHB 134 +#define RSTN_U0_CDN_USB_AXI 135 +#define RSTN_U0_CDN_USB_APB 136 +#define RSTN_U0_CDN_USB_UTMI_APB 137 +#define RSTN_U0_CDN_USB_PWRUP 138 +#define RSTN_U0_PLDA_PCIE_AXI_MST0 139 +#define RSTN_U0_PLDA_PCIE_AXI_SLV0 140 +#define RSTN_U0_PLDA_PCIE_AXI_SLV 141 +#define RSTN_U0_PLDA_PCIE_BRG 142 +#define RSTN_U0_PLDA_PCIE_CORE 143 +#define RSTN_U0_PLDA_PCIE_APB 144 +#define RSTN_U1_PLDA_PCIE_AXI_MST0 145 +#define RSTN_U1_PLDA_PCIE_AXI_SLV0 146 +#define RSTN_U1_PLDA_PCIE_AXI_SLV 147 +#define RSTN_U1_PLDA_PCIE_BRG 148 +#define RSTN_U1_PLDA_PCIE_CORE 149 +#define RSTN_U1_PLDA_PCIE_APB 150 +/* + * group[5]: aoncrg + */ +#define RSTN_U0_DW_GMAC5_AXI64_AXI 160 +#define RSTN_U0_DW_GMAC5_AXI64_AHB 161 +#define RSTN_U0_AON_IOMUX_PRESETN 162 +#define RSTN_U0_PMU_APB 163 +#define RSTN_U0_PMU_WKUP 164 +#define RSTN_U0_RTC_HMS_APB 165 +#define RSTN_U0_RTC_HMS_CAL 166 +#define RSTN_U0_RTC_HMS_OSC32K 167 +/* + * group[6]: ispcrg + */ +#define RSTN_U0_ISPV2_TOP_WRAPPER_P 192 +#define RSTN_U0_ISPV2_TOP_WRAPPER_C 193 +#define RSTN_U0_M31DPHY_HW 194 +#define RSTN_U0_M31DPHY_B09_ALWAYS_ON 195 +#define RSTN_U0_VIN_N_PCLK 196 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF0 197 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF1 198 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF2 199 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF3 200 +#define RSTN_U0_VIN_N_SYS_CLK 201 +#define RSTN_U0_VIN_P_AXIRD 202 +#define RSTN_U0_VIN_P_AXIWR 203 +/* + * group[7]: voutcrg + */ +#define RSTN_U0_DC8200_AXI 224 +#define RSTN_U0_DC8200_AHB 225 +#define RSTN_U0_DC8200_CORE 226 +#define RSTN_U0_CDNS_DSITX_DPI 227 +#define RSTN_U0_CDNS_DSITX_APB 228 +#define RSTN_U0_CDNS_DSITX_RXESC 229 +#define RSTN_U0_CDNS_DSITX_SYS 230 +#define RSTN_U0_CDNS_DSITX_TXBYTEHS 231 +#define RSTN_U0_CDNS_DSITX_TXESC 232 +#define RSTN_U0_HDMI_TX_HDMI 233 +#define RSTN_U0_MIPITX_DPHY_SYS 234 +#define RSTN_U0_MIPITX_DPHY_TXBYTEHS 235 + +#define RSTN_JH7110_RESET_END 236 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ |