board:starfive: add clk init

Add clk init for ddr on JH7110 board

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>

3 files changed, 58 insertions, 30 deletions

diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
index 89724813d8..4f7bcc5ee1 100755
--- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
+++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
@@ -9,11 +9,13 @@
 #define __STARFIVE_JH7110_REGS_H
 
 /*system control register*/
-#define STG_SYSCON_BASE          0x10240000
-#define SYS_SYSCON_BASE          0x13030000
-#define SYS_IOMUX_BASE           0x13040000
-#define AON_SYSCON_BASE          0x17010000
-#define SYS_CRG_BASE			0x13020000
+#define STG_SYSCON_BASE	0x10240000
+#define SYS_SYSCON_BASE	0x13030000
+#define SYS_IOMUX_BASE		0x13040000
+#define AON_SYSCON_BASE	0x17010000
+#define SYS_CRG_BASE		0x13020000
+#define AON_CRG_BASE		0x17000000
+#define STG_CRG_BASE		0x10230000
 #define CLK_ENABLE_MASK		0x80000000U
 #define SYS_CRG_RESET_ASSERT3_SHIFT	0X304U
 #define SYS_CRG_RESET_STATUS3_SHIFT	0X314U
@@ -57,5 +59,25 @@
 #define TIMER_RSTN_TIMER2_SHIFT	24
 #define TIMER_RSTN_TIMER3_SHIFT	25
 
+#define CLK_CPU_ROOT_OFFSET	0x0
+#define CLK_CPU_ROOT_SW_SHIFT	24
+#define CLK_CPU_ROOT_SW_MASK	0x1000000U
+
+#define CLK_BUS_ROOT_OFFSET	0x14
+#define CLK_BUS_ROOT_SW_SHIFT	24
+#define CLK_BUS_ROOT_SW_MASK	0x1000000U
+
+#define CLK_NOC_BUS_STG_AXI_OFFSET	0x180
+#define CLK_NOC_BUS_STG_AXI_EN_SHIFT	31
+#define CLK_NOC_BUS_STG_AXI_EN_MASK	0x80000000U
+
+#define CLK_AON_APB_FUNC_OFFSET	0x4
+#define CLK_AON_APB_FUNC_SW_SHIFT	24
+#define CLK_AON_APB_FUNC_SW_MASK	0x1000000U
+
+#define CLK_QSPI_REF_OFFSET	0x168
+#define CLK_QSPI_REF_SW_SHIFT	24
+#define CLK_QSPI_REF_SW_MASK	0x1000000U
+
 #endif /* __STARFIVE_JH7110_REGS_H */
 
diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c
index 44d2a4cc77..21ce5d12c1 100644
--- a/board/starfive/evb/spl.c
+++ b/board/starfive/evb/spl.c
@@ -7,12 +7,15 @@
 
 #include <common.h>
 #include <init.h>
-#include <spl.h>
-#include <log.h>
-#include <linux/delay.h>
-#include <image.h>
 #include <asm/arch/spl.h>
 #include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/jh7110-regs.h>
+#include <image.h>
+#include <linux/bitops.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <spl.h>
 
 #define MODE_SELECT_REG		0x1702002c
 
@@ -59,6 +62,30 @@ void board_init_f(ulong dummy)
 {
 	int ret;
 
+	/*DDR control depend clk init*/
+	clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
+		BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK);
+
+	clrsetbits_le32(SYS_CRG_BASE + CLK_BUS_ROOT_OFFSET,
+		CLK_BUS_ROOT_SW_MASK,
+		BIT(CLK_BUS_ROOT_SW_SHIFT) & CLK_BUS_ROOT_SW_MASK);
+
+	clrsetbits_le32(SYS_CRG_BASE + CLK_NOC_BUS_STG_AXI_OFFSET,
+		CLK_NOC_BUS_STG_AXI_EN_MASK,
+		BIT(CLK_NOC_BUS_STG_AXI_EN_SHIFT)
+		& CLK_NOC_BUS_STG_AXI_EN_MASK);
+
+	clrsetbits_le32(AON_CRG_BASE + CLK_AON_APB_FUNC_OFFSET,
+		CLK_AON_APB_FUNC_SW_MASK,
+		BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK);
+
+	clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
+		CLK_QSPI_REF_SW_MASK,
+		BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
+
+	/*set GPIO to 1.8v*/
+	setbits_be32(SYS_SYSCON_BASE + 0xC, 0xf);
+
 	ret = spl_early_init();
 	if (ret)
 		panic("spl_early_init() failed: %d\n", ret);
diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c
index aa3899c03b..3253f02c60 100644
--- a/board/starfive/evb/starfive_evb.c
+++ b/board/starfive/evb/starfive_evb.c
@@ -17,27 +17,6 @@
 #include <linux/bitops.h>
 #include <asm/arch/gpio.h>
 
-#define SYS_IOMUX_DOEN(gpio, oen) \
-	clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \
-		GPIO_DOEN_MASK <<  GPIO_SHIFT(gpio), \
-		(oen) << GPIO_SHIFT(gpio))
-
-#define SYS_IOMUX_DOUT(gpio, gpo) \
-	clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\
-		GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\
-		((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
-
-#define SYS_IOMUX_DIN(gpio, gpi)\
-	clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\
-		GPIO_DIN_MASK << GPIO_SHIFT(gpi),\
-		((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
-
-#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\
-		SYS_IOMUX_DOEN(gpio, oen);\
-		SYS_IOMUX_DOUT(gpio, gpo);\
-		SYS_IOMUX_DIN(gpio, gpi); \
-	} while (0)
-
 #define SYS_CLOCK_ENABLE(clk) \
 	setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)