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| author | samin <samin.guo@starfivetech.com> | 2022-05-23 12:00:43 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:36 +0300 |
| commit | 1f6321dbaf5951fd0ffce1bf320000c8be9280f6 (patch) | |
| tree | 86d220d33d6cc9f80fa53aa897a1120c8c765c9f | |
| parent | fc05902d00e58c4c85a34d8ab44dc42eef51cdc6 (diff) | |
| download | u-boot-1f6321dbaf5951fd0ffce1bf320000c8be9280f6.tar.xz | |
spl: satrfive: bus_root switch to pll2.
High-speed emmc/sdio support
Signed-off-by: samin <samin.guo@starfivetech.com>
| -rwxr-xr-x | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 5 | ||||
| -rw-r--r-- | board/starfive/evb/spl.c | 4 |
2 files changed, 0 insertions, 9 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index 8307b0ef0d..7ebe23adef 100755 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -82,11 +82,6 @@ #define CLK_QSPI_REF_SW_SHIFT 24 #define CLK_QSPI_REF_SW_MASK 0x1000000U -#define CLK_SDIO_SOURCEMUX_OFFSET 0x14 -#define CLK_SDIO_SCLK_SW_SHIFT 24 -#define CLK_SDIO_SCLK_SW_MASK 0x1000000U - - #define PLL0_DACPD_SHIFT 0x18U #define PLL0_DACPD_MASK 0x1000000U #define PLL0_DSMPD_SHIFT 0x19U diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c index 0de246557b..b683786d28 100644 --- a/board/starfive/evb/spl.c +++ b/board/starfive/evb/spl.c @@ -116,10 +116,6 @@ void board_init_f(ulong dummy) CLK_QSPI_REF_SW_MASK, (0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK); - clrsetbits_le32(SYS_CRG_BASE + CLK_SDIO_SOURCEMUX_OFFSET, - CLK_SDIO_SCLK_SW_MASK, - (0 << CLK_SDIO_SCLK_SW_SHIFT) & CLK_SDIO_SCLK_SW_MASK); - /*set GPIO to 1.8v*/ setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf); |