diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-14 10:32:55 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:35 +0300 |
| commit | 76c3fe38884eabb095547ea5fd633855f221a2c5 (patch) | |
| tree | 1330905d87bc3b9e91b48b802bcc3d88a04ac20b | |
| parent | f785501c47181e5918e8464edfedfee3a1c43566 (diff) | |
| download | u-boot-76c3fe38884eabb095547ea5fd633855f221a2c5.tar.xz | |
clk:starfive-jh7110: Update pll0/pll1/pll2 clk
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define
from clk-jh7110.c to jh7110_clk.dts
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 6 | ||||
| -rw-r--r-- | arch/riscv/dts/jh7110_clk.dtsi | 19 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110.c | 10 |
3 files changed, 29 insertions, 6 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index a7952031ce..1b570148ef 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -785,12 +785,14 @@ "tx", "ptp_ref", "stmmaceth", - "pclk"; + "pclk", + "gtxc"; clocks = <&clkgen JH7110_GMAC0_GTXCLK>, <&clkgen JH7110_U0_GMAC5_CLK_TX>, <&clkgen JH7110_GMAC0_PTP>, <&clkgen JH7110_U0_GMAC5_CLK_AHB>, - <&clkgen JH7110_U0_GMAC5_CLK_AXI>; + <&clkgen JH7110_U0_GMAC5_CLK_AXI>, + <&clkgen JH7110_GMAC0_GTXC>; resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>, <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>; reset-names = "ahb", "stmmaceth"; diff --git a/arch/riscv/dts/jh7110_clk.dtsi b/arch/riscv/dts/jh7110_clk.dtsi index d67134fa8a..fce9df8419 100644 --- a/arch/riscv/dts/jh7110_clk.dtsi +++ b/arch/riscv/dts/jh7110_clk.dtsi @@ -112,6 +112,23 @@ #clock-cells = <0>; clock-frequency = <297000000>; }; - /* external clocks end */ + + pll0_out: pll0_out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + pll1_out: pll1_out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1066000000>; + }; + + pll2_out: pll2_out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1228800000>; + }; }; diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index b26144ca0f..bad022f6e7 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -49,7 +49,7 @@ static const char *bus_root_sels[2] = { static const char *qspi_ref_sels[2] = { [0] = "osc", - [1] = "clk_qspi_ref_src", + [1] = "u0_cdns_qspi_ref_src", }; static const char *gmac5_tx_sels[2] = { @@ -303,7 +303,7 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg, static int jh7110_clk_init(struct udevice *dev) { struct jh7110_clk_priv *priv = dev_get_priv(dev); - +#if 0 clk_dm(JH7110_PLL0_OUT, starfive_clk_fix_factor(priv->sys, "pll0_out", "osc", 52, 1)); @@ -313,7 +313,7 @@ static int jh7110_clk_init(struct udevice *dev) clk_dm(JH7110_PLL2_OUT, starfive_clk_fix_factor(priv->sys, "pll2_out", "osc", 51, 1)); - +#endif /*root*/ clk_dm(JH7110_CPU_ROOT, starfive_clk_mux(priv->sys, "cpu_root", @@ -474,6 +474,10 @@ static int jh7110_clk_init(struct udevice *dev) clk_dm(JH7110_GMAC0_PTP, starfive_clk_gate_divider(priv->sys, "gmac0_ptp", "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5)); + clk_dm(JH7110_GMAC0_GTXC, + starfive_clk_gate(priv->sys, + "gmac0_gtxc", "gmac0_gtxclk", + SYS_OFFSET(JH7110_GMAC0_GTXC))); /*UART0*/ clk_dm(JH7110_UART0_CLK_APB, starfive_clk_gate(priv->sys, |