diff options
| author | Koji Matsuoka <koji.matsuoka.xm@renesas.com> | 2020-07-21 09:21:53 +0300 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-06-24 21:22:18 +0300 |
| commit | b3494132f068906a73e86826ffb7b19f4ad5ec5f (patch) | |
| tree | 127c10c378a195ef3f42df7df1797325febab970 | |
| parent | 4cfdcf39482640527e6ca8e8c092a43bff3599c4 (diff) | |
| download | u-boot-b3494132f068906a73e86826ffb7b19f4ad5ec5f.tar.xz | |
ARM: renesas: Add generic timer initialization for V3U Falcon
Init the Generic Timer for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| -rw-r--r-- | board/renesas/falcon/falcon.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index 3e591e4b42..c3241bc21d 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -20,6 +20,31 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGWPR 0xE6150000 #define CPGWPCR 0xE6150004 +#define EXTAL_CLK 16666600u +#define CNTCR_BASE 0xE6080000 +#define CNTFID0 (CNTCR_BASE + 0x020) +#define CNTCR_EN BIT(0) + +static void init_generic_timer(void) +{ + u32 freq; + + /* Set frequency data in CNTFID0 */ + freq = EXTAL_CLK; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +void s_init(void) +{ + init_generic_timer(); +} + int board_early_init_f(void) { /* Unlock CPG access */ |